TDA2SA datasheet(350/427 Pages) TI2

350 / 427 page

350

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

•

“Loss of Input Power” early warning.

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by using the First Stage

Converter’s (i.e. LM536033-Q1) Power Good status output to enable and disable the Second Stage

PMIC devices (i.e. TPS65917/919, LP8733, and LP8732). If a different First Stage Converter is

used, care must be taken to ensure an adequate “PG_Status” or “Vbatt_Status” signal is provided

that can disable Second Stage PMIC to begin a controlled and compliant SoC power down

sequence. The total elapsed time from asserting “PG_Status” low until SoC’s PMIC input voltage

reaches minimum level of 2.75 V should be minimum of 1.5 ms and 2 ms preferred.

•

Maximize discharge time of First Stage Vout (VSYS_3V3 power rail = input voltage to SoC PMIC).

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by opening an in-line load

switch immediately upon “PG_Status” low assertion in order to remove the SoC’s 3.3 V IO load

current from VSYS_3V3. This will extend the VSYS_3V3 power rail’s discharge time in order to

maximize elapsed time for allowing SoC PMIC to execute a controlled and compliant power down

sequence. Care should be taken to either disable or isolate any additional peripheral components

that may be loading the VSYS_3V3 rail as well.

•

Sufficient bulk decoupling capacitance on the First Stage Vout (VSYS_3V3 per PDN) that allows for

desired 1.5 – 2 ms elapsed time as described above.

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by using 200 μF of total

capacitance on VSYS_3V3. The First Stage Converter (i.e. LM536033-Q1) can typically drive a

max of 400 μF to help extend VSYS_3V3 discharge time for a compliant SoC power down

sequence.

•

Optimizing the Second Stage SoC PMIC’s OTP settings that determines SoC power up and down

sequences and total elapsed time needed for a controlled sequence.

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by using optimized OTPs per

the SCH and components used. The definition of these OTPs is captured in the detailed timing

diagrams for both power up and down sequences. The PDN diagram typically shows a

recommended PMIC OTP ID based upon the SoC and DDR memory types.

8.3.8

Example PCB Design

The following sections describe an example PCB design and its resulting PDN performance for the

vdd_mpu key processor power domain.

8.3.8.1

Example Stack-up

Layer Assignments:

•

Layer Top: Signal and Segmented Power Plane

–

Processor and PMIC components placed on Top-side

•

Layer 2: Gnd Plane1

•

Layer 3: Signals

•

Layer n: Power Plane1

•

Layer n+1: Power Plane 2

•

Layer n+2: Signal

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Layer n+3: Gnd Plane2

•

Layer Bottom: Signal and Segmented Power Planes

–

Decoupling caps, etc.

Via Technology: Through-hole

Copper Weight:

•

½ oz for all signal layers.

•

1-2oz for all power plane for improved PCB heat spreading.

•

Total PCB Thickness 0.080inches.

TDA2SA Datasheet(PDF) 350 Page - Texas Instruments

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