TDA2SA datasheet(348/427 Pages) TI2

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348

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

NOTE

For power IC which can support more than 10µF close to processor, a bulk capacitor of at

least 22µF is strongly recommended for VDD_MPU power domains.

8.3.5

Power Supply Mapping

TPS65917 or TPS659039 are the Power Management ICs (PMICs) that should be used for the Device

designs. TI requires use of these PMICs for the following reasons:

•

TI has validated their use with the Device

•

Board level margins including transient response and output accuracy are analyzed and optimized for

the entire system

•

Support for power sequencing requirements (refer to Section 5.9 Power Supply Sequences)

•

Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software

Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the

most stringent of the rails combined should be implemented for the particular supply rail.

It is possible that some voltage domains on the device are unused in some systems. In such cases, to

ensure device reliability, it is still required that the supply pins for the specific voltage domains are

connected to some core power supply output.

These unused supplies though can be combined with any of the core supplies that are used (active) in the

system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,

thereby having a single power supply driving the combined CORE, IVA and GPU domains.

For the combined rail, the following relaxations do apply:

•

The AVS voltage of active rail in the combined rail needs to be used to set the power supply

•

The decoupling capacitance should be set according to the active rail in the combined rail

Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS

outputs of the TPS659039 PMIC.

Table 8-4. TPS659039 Power Supply Connections(1)

SMPS

Valid Combination

Reference Platform

Valid Combination

MPU Centric

Valid Combination

DSPEVE Centric(3)

Valid Combination

IVA Centric

TPS659039 Current

Rating Limitation (4)

(5)

SMPS1/2/3(2)

vdd_mpu

vdd_mpu, vdd_gpu,

vdd_iva

vdd_mpu

SMPS1/2: 6A

SMPS1/2/3: 9A

SMPS3(2)

vdds_ddr1

SMPS3: 3A

SMPS4/5

vdd_dspeve

vdd_dspeve,

vdd_gpu, vdd_iva

vdd_dspeve

vdd_dspeve,

vdd_gpu

SMPS4/5: 4A

SMPS6

vdd_gpu

vdd

SMPS6: 2-3A

(BOOST_CURRENT

=0/1)

SMPS7

vdd

Free

SMPS8

vdd_iva

Free

vdd_iva

SMPS9

vdds18v

(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and

peak) is within the limits of the PMIC for all rails of the device

(2) Dual phase (SMPS1/2) can be used as long as the peak power consumption is maintained below the SMPS1/2 capacity

For the latest rated output current specifications for the TPS659039 device, please refer to the PMIC data manual.

MPU power consumption is highly system dependent. A detailed power consumption estimate must be performed to confirm

compatibility. Example: Single vs Dual MPU, OPP_NOM vs OPP_OD vs OPP_HIGH, TPS659039 configured with VI≥3V vs VI<3V,

etc. Contact your TI representative for details.

(3) Combination 3 must only be used in systems where the MPU frequency is 1 GHz or lower. If greater than 1 GHz MPU is required, then

the vdd_mpu domain must be powered independently.

TDA2SA Datasheet(PDF) 348 Page - Texas Instruments

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