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TDA2SA Datasheet(PDF) 415 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 415 Page - Texas Instruments |
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415 / 427 page  DQLMX3 DQLMY0 DQLMY3 DQLMY2 DB3 DQLMX2 DB2 3 2 1 DQ[23:31]/DM3/DQS3 0 DQ[16:23]/DM2/DQS2 DQLMX1 DB1 DB0 DQLMX0 DQ[8:15]/DM1/DQS1 DQ[0:7]/DM0/DQS0 DQLMY1 DB0 - DB3 represent data bytes 0 - 3. 415 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Applications, Implementation, and Layout Copyright © 2015–2019, Texas Instruments Incorporated There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore: DQLM0 = DQLMX0 + DQLMY0 DQLM1 = DQLMX1 + DQLMY1 DQLM2 = DQLMX2 + DQLMY2 DQLM3 = DQLMX3 + DQLMY3 Figure 8-84. DQLM for Any Number of Allowed DDR3 Devices Table 8-53. Data Routing Specification(2) NO. PARAMETER MIN TYP MAX UNIT DRS31 DB0 length 340 ps DRS32 DB1 length 340 ps DRS33 DB2 length 340 ps DRS34 DB3 length 340 ps DRS35 DBn skew(3) 5 ps DRS36 DQSn+ to DQSn- skew 1 ps DRS37 DQSn to DBn skew(3)(4) 5(10) ps DRS38 Vias per trace 2(1) vias DRS39 Via count difference 0(10) vias DRS310 Center-to-center DBn to other DDR3 trace spacing(6) 4 w(5) DRS311 Center-to-center DBn to other DBn trace spacing(7) 3 w(5) DRS312 DQSn center-to-center spacing(8) (9) DRS313 DQSn center-to-center spacing to other net 4 w(5) (1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation. (2) External termination disallowed. Data termination should use built-in ODT functionality. (3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended. (4) Each DQS pair is length matched to its associated byte. (5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length. (6) Other DDR3 trace spacing means other DDR3 net classes not within the byte. (7) This applies to spacing within the net classes of a byte. (8) DQS pair spacing is set to ensure proper differential impedance. (9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo. (10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded. |
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