TDA2SA datasheet(129/427 Pages) TI2

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TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

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SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Terminal Configuration and Functions

Table 4-24. PRCM Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

BALL

clkout2

Device Clock output 2. Can be used externally for devices with non-

critical timing requirements, or for debug.

D18/ N1

clkout3

Device Clock output 3. Can be used externally for devices with non-

critical timing requirements, or for debug.

C23

rstoutn

Reset out (Active low) output is asserted low whenever any global reset

condition exists. After a brief delay, it will be set high upon removal of the

internal global reset condition (porz, warm reset). It is only functional

after its output buffer’s reference voltage (vddshv3) is valid. If it is used

as a reset for device peripheral components, then it should be AND

gated with porz to avoid the possibility of reset signal glitches during a

power up sequence.(2)

F23

resetn

Reset (active low) input’s falling edge can trigger a device warm reset

state from an external component. This signal should be high prior to or

simultaneous with, porz rising. If the signal is not used in the system,

resetn should be pulled high with an external pull-up resistor to vddshv3.

E23

porz

Power on Reset (active low) input must be asserted low during a device

power up sequence or cold reset state when all supplies are disabled.

Typically, an external PMIC is the source and sets porz high after all

supplies reach valid operating levels. Asserting porz low puts the entire

device in a safe reset state.

F22

xref_clk0

External Reference Clock 0. For Audio and other Peripherals.

D18

xref_clk1

External Reference Clock 1. For Audio and other Peripherals.

E17

xref_clk2

External Reference Clock 2. For Audio and other Peripherals.

B26

xref_clk3

External Reference Clock 3. For Audio and other Peripherals.

C23

xi_osc0

System Oscillator OSC0 Crystal input / LVCMOS clock input. Functions

as the input connection to a crystal when the internal oscillator OSC0 is

used. Functions as an LVCMOS-compatible input clock when an external

oscillator is used

AE15

xo_osc0

System Oscillator OSC0 Crystal output

AD15

xi_osc1

Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input. Functions

as the input connection to a crystal when the internal oscillator OSC1 is

used. Functions as an LVCMOS-compatible input clock when an external

oscillator is used

AC15

xo_osc1

Auxiliary Oscillator OSC1 Crystal output

AC13

RMII_MHZ_50_CLK(1)

RMII Reference Clock (50MHz). This pin is an input when external

reference is used or output when internal reference is used.

(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the

clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.

(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it

must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.

4.4.20.3 Real Time Clock (RTC) Interface

NOTE

For more information, see the Real Time Clock (RTC) SS section of the device TRM.

Table 4-25. RTC Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

Wakeup0

RTC External Wakeup Input 0

AD17

Wakeup1

RTC External Wakeup Input 1

AC17

Wakeup2

RTC External Wakeup Input 2

AB16

Wakeup3

RTC External Wakeup Input 3

AC16

rtc_porz

RTC Power Domain Power-On Reset Input

AB17

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