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INA849 Datasheet(PDF) 29 Page - Texas Instruments |
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INA849 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 39 page  8.4.2 Layout Example GND GND GND IN– 4 IN+ 1 2 3 FDA_IN+ OUT– OUT+ 9 FDA_IN– 12 11 10 PAD R2 GND IN+ R1 GND C4 C2 C7 C6 VOCM ADC_INP ADC_INN Use ground pours for shielding the input signal pairs Place bypass capacitors as close to IC as possible R3 R4 C10 Consider using thermal vias for heatsinking Cutouts on ground planes underneath input pins can reduce stray capacitance, for better phase margin C8 C9 GND VIN+ VIN R2 R1 C2 C5 PGA854 ADC C6 C7 INP INN C10 R3 R4 OUT+ OUT VCM C9 C8 Connect feedback capacitors between OUT and FDA_IN+ (optional) A<2:0> DGND IN- A2 A0 C1 GND LVSS VS C3 C5 VS+ LVDD Optional noise filtering capacitors C4 C1 C3 VS+ VS VLVDD VLVSS Figure 8-10. Example Schematic and Associated PCB Layout www.ti.com PGA854 SBOSAN2A – AUGUST 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: PGA854 |
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