MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER

MP8007 Rev.1.0

www.MonolithicPower.com

15

6/27/2016

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20.5V.

MP8007

presents

a

current

in

classification mode as showing in Table 1.

Table 1– CLASS Resistor Selection

Class

Max. Input

Power to

PD (W)

Classification

Current (mA)

RCLASS

(Ω)

0

12.95

2

578

1

3.84

10.55

110

2

6.49

18.7

62

3

12.95

28.15

41.2

4

25.5

40.4

28.7

2-Event Classification

MP8007 can be used as a Type-1 PD as class

0–3 in Table 1, it also distinguishes class 4 with

2-event

classification.

Generally

it

is

recommended to set MP8007 in class 0-3

because the DCDC converter can only deal

with 13W power.

In 2-event classification, the Type-2 PSE reads

the power classification twice. Figure 2 presents

an example of a 2-event classification. The first

classification event occurs when the PSE

presents a voltage between 14.5V-to-20.5V to

MP8007 and the MP8007 presents a class 4

loads current. The PSE then drops the input

voltage into the mark voltage range of 6.9V to

10.1V, signaling the first mark event. MP8007

presents a load current between 0.5mA to 2mA

in the mark event voltage range

The PSE repeats this sequence, signaling the

second classification and second mark event.

The PSE then applies power to MP8007 and

MP8007 charges up the DCDC input capacitor

CBULK (C1 of schematic on page 1) with a

controlled inrush current. When CBULK is fully

charged, the T2P pin presents an active low

signal with respect to VSS after TDELAY. The T2P

output becomes inactive when the MP8007

input voltage VDD falls below UVLO as figure 3

work flow shows. With class 0-3 setting in

MP8007, 2-event classification and T2P can be

ignored.

PD Interface UVLO and Current Limit

When PD is powered by PSE and VDD is

higher than turn on threshold, the Hot-swap

switch will start pass a limited current IINRUSH to

charge the down stream DC-to-DC converter’s

input capacitor CBULK. The startup charging

current is around 120mA.

If RTN drops to lower than 1.2V, the hot-swap

current limit will change to 840mA. After the

TDELAY from UVLO starting, MP8007 will assert

PG signal and go from the startup mode to the

running mode if inrush period elapse, the PG

signal

can

enable

down-stream

DCDC

converter internally.

If VDD-VSS drops below falling UVLO, the Hot-

swap MOSFET and DCDC converter both are

disabled.

If output current overloads on the internal pass

MOSFET, current limit works and VRTN-VSS rises.

If VRTN rises above 10V for longer than 1ms, or

rises above 20V, the current limit reverts to the

inrush value, and PG is pulled down internally

to disable DCDC regulator at the same time.

Figure 3 shows the current limit, PG and T2P

work logic during startup from PSE power

supply.

Figure 3: Startup Sequence