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MP8007 Datasheet(PDF) 14 Page - Monolithic Power Systems

Part # MP8007
Description  Fully-Integrated 802.3af-Compatible PoE PD Interface with 13W Primary-side Regulated Flyback or Buck Converter
PDF  27 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8007 Datasheet(HTML) 14 Page - Monolithic Power Systems

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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
MP8007 Rev.1.0
www.MonolithicPower.com
14
6/27/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
OPERATION
Compared with IEEE802.3af, the IEE802.3at
standard establishes a higher power allocation
for
Power-over-Ethernet
while
maintaining
backwards compatibility with the existing
IEEE802.3af
systems.
Power
Sourcing
Equipments (PSE) and Powered Devices (PD)
are distinguished as Type-1 complying with the
IEEE
802.3af
power
levels,
or
Type-2
complying with the IEEE 802.3at power levels.
IEEE802.3af/at standard establishes a method
of communication between PD and PSE with
detection, classification and mark event.
The MP8007 is one integrated PoE solution
with IEEE 802.3af PD interface and 13W DCDC
converter. The PD interface also has 802.3at
function, but DCDC converter only support 13
W output, so MP8007 is only used for 802.3af
power design. Along with the PSE it operates
as a safety device to supply voltage only when
the power sourcing equipment recognizes a
unique, tightly specified resistance at the end of
an unknown length of Ethernet cable. After
powered from PSE, the MP8007 will regulate
the output voltage based on application with
isolated or non-isolated topology. Figure 1
shows the function diagram of this device, and
Figure 2 shows typical PD interface power
operation sequence.
Figure 2: PD Interface Operation Description
Detection
The RDET connected between DET and VDD pin
is presented as a load to the PSE in the
Detection Mode, when the PSE applies two
“safe” voltages between 2.7V to 10.1V while
measuring the change in current drawn in order
to determine the load resistance. 24.9kΩ(1%)
resistor between VDD and DET pins is
recommended to present one correct signature,
and the valid signature resistance seen from
power interface (PI) is between 23.7kΩ and
26.3kΩ.
The detection resistance seen from PI is the
result of the input bridge resistance in series
with the VDD loading. The input bridge
resistance is partially cancelled by MP8007
effective leakage resistance during detection.
Classification
The classification mode can specify to the PSE
the expected load range of the device under
power, so that the PSE can intelligently
distribute power to as many loads as it can
within its maximum current capability. The
classification mode is active between 14.5V and



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