MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER

MP8007 Rev.1.0

www.MonolithicPower.com

16

6/27/2016

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Wall

Power

Adaptor

Detection

and

Operation

For applications where an auxiliary power

source such as a wall adapter is used to power

the device, the MP8007 features wall power

adapter detection as showing in figure 4. Once

the input voltage (VDD - VSS) exceeds about

11.5V, the MP8007 enable wall adapter

detection. The wall power adapter detection

resistor divider is connected from VDD to

negative terminal of adaptor, and DADP3 is

added for more accurate hysteresis. There is a

-2.3V reference voltage from AUX to VDD for

adaptor detection. The adaptor is detected

when AUX voltage triggers:

ADPUP

DD

AUX

ADP

DADP3

ADPUP

ADPDOWN

R

VV

(V

V

)

2.3V

RR











(1)

Where, VADP is adaptor voltage, VDADP3 is the

zener voltage, RADPUP and RADPDOWN are the

AUX divider resistors from adaptor power.

If applied adapter voltage is much higher than

the design adapter voltage, VDD-VAUX voltage

will be high, if it is higher than 6.5V, the

MP8007 inner circuit will clamp the VDD-VAUX

voltage at 6.5V, then a current will flow out

through the AUX pin, the current should be

limited lower than 3mA by external resistor

(RADPUP/RADPDOWN or RT resistor from the resistor

divider to AUX PIN.)

To make MP8007 work stable with adaptor

power, one Schottky diode DAPD1 (D4 in

schematic on page 1) is required between

negative terminal of adaptor and VSS. DAPD2

(D5 in schematic on page 1) is used to block

reverse current between adaptor and PSE

power source. When a wall adapter is detected,

the internal MOSFET between RTN and VSS

turns off, classification current is disabled and

T2P becomes active. The PG signal is active

when adaptor power is detected, so that it can

enable the downstream DCDC converter even

input hot-swap MOSFET is disabled.

Figure 4: Adaptor Power Detection

Power Good Indicator (PG)

The PG signal is driven by internal current

source. After TDELAY from UVLO starting and

RTN drops to 1.2V, or a wall power adapter is

detected, the PG signal will be pulled high to

indicate power condition and enable the

downstream DCDC converter. Figure 3 shows

the PG logic when powering from PSE, PG will

be high if adaptor is detected.

DCDC Converter Startup and Power Supply

Once PD input overrides its UVLO, it will charge

DCDC converter’s input capacitor (between

VDD and RTN) with PD inrush current limit.

DCDC converter has an internal start-up circuit.

When voltage between VDD and GND is higher

than 4.3 V, the capacitor at VCC is charged

through the internal LDO. Normally VCC is

regulated at 5.4 V (if VDD is high enough). With

the exception of PD interface UVLO, the DCDC

converter has an additional VIN UVLO (11.6V)

and VCC UVLO (4.7V). When VDD-GND is

higher than the 11.6V UVLO, VCC is charged

higher than the 4.7V UVLO, and PG pin is

pulled high by PD interface, DCDC converter

starts switching.

VCC can be powered from the transformer

auxiliary winding to save IC power loss. Refer

to the “Vcc Power Supply Setting” section for

more details.

Flyback and Buck Mode Converter

The DCDC converter supports both flyback and

buck topology applications. Connect MODE to

GND to set the DCDC converter in flyback

mode, and float MODE to set the DCDC

converter in buck mode. MODE is pulled up

internally to VCC through a 1.5µA current source.

Do not connect MODE to VDD externally in