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MP8007 Datasheet(PDF) 25 Page - Monolithic Power Systems |
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MP8007 Datasheet(HTML) 25 Page - Monolithic Power Systems |
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25 / 27 page ![]() MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 25 6/27/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 5. Keep the feedback trace far away from noise sources (such as SW). The trace connecting FB1 should be short. 6. Use a single point connection between power GND and signal GND. Vias around GND and the thermal pad are recommended to lower the die temperature. Refer to Figure 12 for flyback circuit layout, which is referred to schematic on page 1. Figure 12: Recommended flyback layout For buck circuit: 1. Keep the input loop as short as possible between the input capacitor, rectifier diode, SW, and GND plane for minimal noise and ringing. 2. Keep the output loop between the rectifier diode, the output capacitor, and the inductor as short as possible. 3. Place the VCC capacitor close to VCC for the best decoupling. The current setting resistor R3 should be placed as close to ILIM and AGND as possible. 4. Connect the output voltage sense and VDD power supply from the output capacitor with parallel traces. The feedback trace should be far away from noise sources (such as SW). The trace connected to FB2 should be short. The trace for VDD power should be wider. 5. Use a single point connection between power GND and signal GND. Vias around GND and the thermal pad are recommended to lower the die temperature Refer to Figure 13 for buck circuit layout. Via Top Layer Bottom Layer R7 D3 R8 R5 R2 R1 C3 R6 D1 C2 L1 U1 R3 C5 C1 D5 D4 Figure 13: Recommended buck layout Design Example Below is a design example following the application guidelines for the following specifications: Table 2 – Flyback Design Example VDD-VSS 37V–57V (PoE Supply) RDET 24.9kΩ RCLASS 41.2Ω VADAPTER 48V VOUT 12V IOUT 1A The typical application circuit in Figure 14 shows the detailed application schematic, and is the basis for the typical performance waveforms. Typically, the device is powered by PSE (VDD-VSS=48V). When an adapter voltage above than 38.5V presents, the internal MOSFET between RTN and VSS turns off, instead the device is powered by the adapter whatever the PSE voltage is. For more detailed device applications, please refer to the related Evaluation Board Datasheets. |
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