MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER

MP8007 Rev.1.0

www.MonolithicPower.com

24

6/27/2016

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2016 MPS. All Rights Reserved.

Generally, a 15 percent ripple is acceptable.

Buck Inductor Selection

The inductor is required to transfer the energy

between the input source and the output

capacitors. Unlike normal application where

inductors determine the inductor ripple, the

DCDC converter always works in DCM while

VIN, VOUT, and ILIM are constant. The inductor

only determines the speed of the current rising

and falling, which determines the switching

period. The expected maximum frequency can

determine the inductor value using Equation

(26):

IN

OUT

OUT

D1F

IN

D1F

PEAK

SW

(V

V

) (V

V )

1

L

(V

V ) I

F









(26)

FSW is the expected maximum switching

frequency, which should be lower than 200kHz

in general setting.

Converter Output Diode Selection

The output rectifier diode supplies current to the

output capacitor when the internal MOSFET is

off. Use a Schottky diode to reduce loss due to

the diode forward voltage and recovery time.

In isolation application, the diode should be

rated for a reverse voltage greater than

Equation (27):

IN

S

D1

OUT

PD1

P

VN

VV

V

N







(27)

VPD1 can be selected at 40 percent to 100

percent of VOUT + VIN x NS/NP. An RC or RCD

snubber circuit for the output diode D1 is

recommended.

In buck mode, the diode reverse voltage

equates to the input voltage. A 20 percent ~ 40

percent margin is recommended.

In both applications, the current rating should

be higher than the maximum output current.

Converter Dummy Load

When the system operates without a load in

flyback mode, the output voltage rises above

the normal operation voltage because of the

minimum switching frequency limitation. Use a

dummy load for good load regulation. A large

dummy load decreases efficiency, so the

dummy load is a tradeoff between efficiency

and load regulation. For applications using

Figure 14, a minimum load of around 10mA is

recommended.

PCB Layout Guide

A good layout of the PoE front-end and high-

frequency switching power supply is critical.

Poor layout may result in reduced performance,

excessive EMI, resistive loss, and system

instability. For best results, refer to Figure 12

and Figure 13 and follow the guidelines in

below:

For PD interface circuit:

1. All components place must follow power

flow, from RJ-45, Ethernet transformer,

diode bridges, TVS, to 0.1-μF capacitor and

DCDC converter input bulk capacitor.

2. Make all leads as short as possible with

wide power traces.

3. The spacing between VDD (48V) and VSS

must comply with safety standards like

IEC60950.

4. Place the PD interface circuit ground planes

referenced

to

VSS,

while

place

the

switching

converter

ground

planes

referenced to RTN/GND.

5. The exposed PAD must be connected to

GND, it can not be connected to VSS.

6. If adaptor power detection is enabled, the

AUX divider resistor should be close to AUX

pin. And diode D5 (between VSS and RTN)

should be placed close to VSS and RTN.

For flyback circuit:

1. Keep the input loop as short as possible

between the input capacitor, transformer,

SW, and GND plane for minimal noise and

ringing.

2. Keep the output loop between the rectifier

diode, the output capacitor, and the

transformer as short as possible.

3. Keep the clamp loop circuit between D2, C4,

and the transformer as small as possible.

4. Place the VCC capacitor close to VCC for

the best decoupling. The current setting

resistor R3 should be placed as close to

ILIM

and

AGND

as

possible.