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XM33C321ASPZR Datasheet(PDF) 52 Page - Texas Instruments |
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XM33C321ASPZR Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 113 page  over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tCS.LAG CS lag time, Last clock to CS inactive 1 SPI Clock ns tCS.ACC CS access time, CS active to PICO data out 1/2 SPI Clock ns tCS.DIS CS disable time, CS inactive to PICO high inpedance 1 SPI Clock ns tSU.CI POCI input data setup time (1) Delayed sampling enabled 1 ns tHD.CI POCI input data hold time VDD ≥ 2.7V, delayed sampling enabled 20 ns VDD ≥ 1.71V, delayed sampling enabled 25 ns tSU.CI POCI input data setup time (1) VDD ≥ 2.7V, no delayed sampling 18 ns VDD ≥ 1.71V, no delayed sampling 24 ns tHD.CI POCI input data hold time no delayed sampling enabled 0 ns tVALID.CO PICO output data valid time (2) 10 ns tHD.CO PICO output data hold time (3) 6 ns Peripheral tCS.LEAD CS lead-time, CS active to clock VDD ≥ 2.7V 19 ns VDD ≥ 1.71V 22 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out VDD ≥ 2.7V 25 ns VDD ≥ 1.71V 31 ns tCS.DIS CS disable time, CS inactive to POCI high impedance VDD ≥ 2.7V 39 ns VDD ≥ 1.71V 41.5 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 0 ns tVALID.PO POCI output data valid time(2) VDD ≥ 2.7V 19 ns VDD ≥ 1.71V 24 ns tHD.PO POCI output data hold time(3) 5 ns (1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. (2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge (3) Specifies how long data on the output is valid after the output changing SCLK clock edge MSPM33C321A, MSPM33C3219 SLASFB6 – DECEMBER 2025 www.ti.com 52 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: MSPM33C321A MSPM33C3219 |
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