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TAS5822M Datasheet(PDF) 26 Page - Texas Instruments |
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TAS5822M Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 106 page ![]() LRCK/FS (Input) SCLK (Input) DATA (Input) DATA (Output) 0.5*DVDD 0.5*DVDD 0.5*DVDD 0.5*DVDD tSCLKL tSCLKH tLS tSL tSCLK ISU IDH IDFS Figure 6-7. Serial Audio Timing - Target SDA SCL START Repeated START STOP tD-SU tLOW. tSCL-R. tHI. tS-HD. tBUF. tSCL-F. tD-HD tRS-HD tRS-SU tSDA-R tSDA-F tP-SU tSP Figure 6-8. I2C Communication Timing - Target 6.3.5 Digital Audio Processing TAS5802 DSP has a flexible process flows for different applications, refer to application note, TAS5815 and TAS5802 Process Flows for details. 6.3.6 Class D Audio Amplifier Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D amplifier section of the device. The switching rate of the amplifier is configurable via I2C interface. In this case, the PWM switching frequency is a multiple of the sample rate. TAS5802 SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025 www.ti.com 26 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TAS5802 |
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