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IMXRT1160AXEC Datasheet(PDF) 59 Page - NXP Semiconductors |
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IMXRT1160AXEC Datasheet(HTML) 59 Page - NXP Semiconductors |
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59 / 130 page ![]() Electrical characteristics i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 4, 06/2025 NXP Semiconductors 59 4.4.4 SWD timing parameters Figure 15 depicts the SWD timing. Figure 15. SWD timing Table 44. JTAG timing parameters ID Parameter Value Unit Min Max J0 TCK frequency — 25 MHz J1 TCK cycle time 40 — ns J2 TCK pulse width 20 — ns J3 Input data setup time 5 — ns J4 Input data hold time 5 — ns J5 Output data valid time — 15.2 ns J6 Output high impedance time — 15.2 ns J7 TRST_B assert time 100 — ns J8 TRST_B setup time to TCK edge 18 — ns |
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