IMXRT1160AXEC datasheet(92/130 Pages) NXP

92 / 130 page

i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 4, 06/2025

NXP Semiconductors

Electrical characteristics

4.9.3.2

eMMC4.4/4.41/SD3.0 (Dual Data Rate) AC timing)

Figure 42 depicts the timing of eMMC4.4/4.41/SD3.0. Table 87 lists the eMMC4.4/4.41/SD3.0 timing

characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

Table 86. SD/eMMC4.3 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP1

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP2

2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0

–25 MHz. In high-speed mode,

clock frequency can be any value between 0

–50 MHz.

25/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP3

3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0

–20 MHz. In high-speed mode, clock

frequency can be any value between 0

–52 MHz.

20/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

—

SD3

Clock High Time

tWH

—

SD4

Clock Rise Time

tTLH

—

SD5

Clock Fall Time

tTHL

—

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6

uSDHC Output Delay

tOD

-6.6

3.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7

uSDHC Input Setup Time

tISU

2.5

—

SD8

uSDHC Input Hold Time4

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

tIH

1.5

—

IMXRT1160AXEC Datasheet(PDF) 92 Page - NXP Semiconductors

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