IMXRT1160AXEC datasheet(73/130 Pages) NXP

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Electrical characteristics

i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 4, 06/2025

NXP Semiconductors

4.6.1.4

MIPI LP-CD specifications

4.6.1.5

MIPI DC specifications

4.6.2

CMOS Sensor Interface (CSI) timing parameters

The following sections describe the CSI timing in gated and ungated clock modes.

4.6.2.1

Gated clock mode timing

Figure 29 and Figure 30 shows the gated clock mode timings for CSI, and Table 70 describes the timing

parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC

TMIN-RX3

Minimum pulse width response

—

VINT

Peak Interference amplitude

—

200

fINT

Interference frequency

450

—

MHz

1 Time-voltage integration of a spike above VIL when being in LP-0 state or below VIH when being in LP-1 state.

2 An impulse below this value will not change the receiver state.

3 An input pulse greater than this value will toggle the output.

Table 68. MIPI contention detector DC specifications

Symbol

Parameter

Min

Typ

Max

Unit

VIHCD

Logic 1 contention threshold

450

—

VILCD

Logic 0 contention threshold

—

200

Table 69. MIPI input characteristics DC specifications

Symbol

Parameter

Min

Typ

Max

Unit

VPIN

Pad signal voltage range

-50

—

1350

ILEAK1

1 When the pad voltage is within the signal voltage range between VGNDSH(min) to VOH + VGNDSH(max) and the Lane Module is

in LP receive mode.

Pin leakage current

-10

—



VGNDSH

Ground shift

-50

—

VPIN(absmax)2

2 This value includes ground shift.

Maximum pin voltage level

-0.15

—

1.45

TVPIN(absmax)3

3 The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20 ns window after any LP-0 to LP-1

transition or vice versa. For all other situations it must stay within the VPIN range.

Maximum transient time above VPIN(max) or below VPIN(min)

—

Table 67. MIPI low power receiver AC specifications (continued)

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