DA9080 datasheet(40/72 Pages) RENESAS

40 / 72 page

DA9080 Datasheet

R16DS0519EJ0340 Rev. 3.4

Mar 24, 2025

CFR0011-120-00

Page 40

9.2

Fault Protection

9.2.1

Over-Voltage, Under-Voltage, and Over-Current Protection

Each buck has over-voltage (OV), under-voltage (UV), and over-current (OC) fault protection.

Each buck has a current limit, IPOSLIM. When the current limit is reached, the BUCK<x>_OC_EVENT bit in the

PMC_CH_OC register is set to 0x1. Although the shutdown operation is not executed by the OC fault protection,

if the current is exceeding IPOSLIM, the output voltage falls below VTHR_UVP_FALL.

When the buck output drops below VTHR_UVP_FALL, or increases above VTHR_OVP_RISE, the BUCK<x>_PG_STAT bit

in the PMC_PGOOD_UV register is set to 0x0. Additionally, BUCK<x>_UV_EVENT, or BUCK<x>_OV_EVENT,

bit is set as 0x1 in its respective register. (PMC_CH_UV or PMC_CH_OV).

The LDO has under-voltage (UV) and over-current (OC) fault protection. When either of these conditions are

met, status bits are set to 0x1 in dedicated registers, in a similar way to the bucks.

A supply voltage fault condition, on any supply, causes a power down and all supplies are disabled. The

sequencer is run with reverse slot order. Supplies assigned to slot four are disabled first.

A re-start is initiated, after a blanking time, with a hiccup behavior. The outputs are discharged by the internal

pull-down resistors prior to being enabled again.

The UV, OV and OC register bits are sticky and remain set through a hiccup cycle, see Figure 44. The register

bits are only cleared on a register write of 1.

9.2.2

Thermal Shutdown

DA9080 also has a thermal shutdown (TSD) function. When the die temperature goes above 140 °C (typ)

(TTHR_SHDN), all the regulator outputs and the GPADC are shutdown. The sequencer is run with reverse slot

order. Supplies assigned to slot four are disabled first.

The TSD event is recorded in a register OVERTEMP_EVENT bit<7> in PMC_CH_OC (0x01).

When the die temperature goes below 125 °C(typ), the start-up sequence is restarted.

Note that the I2C communication is halted during TSD, the OVERTEMP_EVENT bit cannot be read back at this

time. The host should check the OVERTEMP_EVENT bit after the device has recovered from TSD. The

OVERTEMP_EVENT bit is sticky and is cleared by over-writing the bit with 1.

DA9080 Datasheet(PDF) 40 Page - Renesas Technology Corp