AD4083 datasheet(23/94 Pages) AD

23 / 94 page

Data Sheet

AD4083

THEORY OF OPERATION

analog.com

Rev. 0 | 23 of 94

measuring the voltage at the reference input pin (REFIN). Each

monitor has its own comparator output that is used to decouple the

analog and digital block resets as shown in Figure 39.

Figure 39. Simplified Diagram of POR Circuit

The core VDD (1.1V) supply monitor compares the VDD11 supply

voltage against a preset threshold of 0.93V. If the supply voltage

falls to less than this threshold, a reset signal, POR_D, asserts.

The digital logic reset signal, DIG_RESET, is defined as the logical

combination of the POR_D signal and (logical AND) the compliment

of the SPI software reset function. When either the POR_D signal

(VDD11 < 0.93V) or the SW RESET signal is asserted, the internal

digital circuitry is held in reset. When cleared, the contents of the

configuration registers are restored to the factory default settings.

The reference monitor compares the input voltage at REFIN against

a preset threshold of 2.7V. As illustrated in Figure 39, power for

the reference monitor circuit is supplied from the VDD33 supply.

However, it is important to note that a reference voltage below

2.6V will cause the device to stop outputting conversion data

results. To recover the conversion process, the reference voltage

needs to be brought to 2.87V. For correct operation of the monitor

circuit, the VDD33 supply must be applied to the AD4083 within

the specified tolerance of 3.3V ± 5% before the reference source

is enabled. Assuming the device is operating within the specified

supply conditions, a reference voltage less than 2.7V results in the

assertion of an internal reset signal, POR_A. The POR_A signal

and (logical AND) the DIG_RESET signal are combined to produce

a reset (ANA_RESET) for the analog circuit blocks including the

ADC core, ADC timer, reference buffer, and so forth. If this reset

signal is asserted, the analog blocks are placed in an inactive state,

and the converter functionality is disabled. This event is indicated

with a value of 1 in the POR_ANA_FLAG bit from the Device

Status Register (Address 0x14). The state of the event detection is

persistent until a Logic 1 is written to the POR_ANA_FLAG bit to

clear the detection state.

POWER SUPPLY SEQUENCE

Table 10 specifies the recommended supply sequences for both

internal and external generation of 1.1V supply rails (IOVDD and

VDD11). Both methods are shown in Figure 40 and Figure 41,

where the supplies that must be provided to the AD4083 are

highlighted in blue, including the REFIN voltage. In both cases, the

AD4083 requires that the supplies are applied in ascending voltage

order. The design must also ensure that voltage is applied at the

analog inputs (IN+ and IN−) and reference input (REFIN) concur-

rently with, or immediately following, the VDD33 supply. Failing in

providing REFIN reference voltage on power up will result in no

ADC conversions at the output of the ADC, and it will continue to do

so until REFIN voltage is provided. Note that test pattern described

in the Data Interface Test Functions section will not work in the pre-

viously mentioned case when a voltage reference is not provided at

the power up. However, if reference voltage was provided at power

up and then removed, the test pattern will still work and output the

correct data. As described in the Power-On Reset (POR) Monitor

section, the voltage at the reference input pin must only be applied

once VDD33 is within the specified supply tolerance to avoid unde-

sired behavior. Therefore, if the selected voltage reference does not

provide an enable pin, it is strongly recommended to design the

reference circuit to power up after VDD33. After reset or POR, there

are 300μs required before the device can be accessed; this is to

assure the device has completed the initialization procedures. If this

condition is not met, NOT_READY_ERR bit will be asserted of the

INTERFACE_STATUS_A (0x11).

The configuration SPI inputs, CS, SCLK, and SDI, are protected

with clamps to the VDD33 supply rail to allow the inputs to swing

more than IOVDD. As a consequence of this architectural decision,

it is necessary to either drive the SPI inputs to ground or to other-

wise leave the inputs floating until VDD33 is greater than IOVDD

− 0.3V. Alternatively, the VDD33 source can be connected to the

device using a series power switch, like the ADP199, configured so

that the switch is open when the source is less than IOVDD − 0.3V,

eliminating the parasitic current path through the digital inputs to

VDD33.

Table 10. Recommended Supply Sequence

1.1V Supplies (IOVDD and VDD11) Source

Supply Sequence

Internally Generated

1. VDDLDO

2. VDD33

3. Digital inputs

4. Input drive, reference

Externally Generated

1. IOVDD, VDD11

2. VDD33

3. Digital inputs

4. Input drive, reference

To power down the application circuit, the power-up sequence

specified in Table 10 should be reversed.

AD4083 Datasheet(PDF) 23 Page - Analog Devices

AD4083 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL