AD4083 datasheet(29/94 Pages) AD

29 / 94 page

Data Sheet

AD4083

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 29 of 94

REFERENCE CIRCUITRY DESIGN

The AD4083 requires a low noise, high precision and stability,

and low temperature drift external reference of 3V. This reference

defines a differential input range for the ADC of ±VREFIN. The refer-

ence must be within ±5mV of +3V. Recommended references are

LTC6655, LT6657, or ADR4530. For best performance, however,

use the LTC6655 external reference. Table 13 details the typical

parameters of the previously mentioned references, comparing

absolute accuracy, noise, temperature drift, load regulation, and

power consumption. For more detailed specifications, refer to the

data sheet of the given product.

Table 13. Comparison of the Main Parameters of the LTC6655, LT6657, and

ADR4530 References

Parameter

LTC6655

LT6657

ADR4530B

Accuracy

0.025%

0.1%

0.02%

Temperature Coefficient

(ppm/°C)

1.5

0.1Hz to 10Hz Noise (ppm p-p) 0.25

0.5

0.53

Maximum Load (mA)

±5

±10

Load Regulation (ppm/mA)

0.7

Maximum Supply (V)

13.2

Shutdown

Yes

Supply Current, IS (mA)

1.2

0.7

There is no need for the external reference capacitor because

the AD4083 embeds one internally, 9.4μF, (see Figure 46). The

REFIN reference input pin is internally buffered, which substantial-

ly reduces ADC conversion transients and isolates the external

reference from these transients. Therefore, no external amplifier is

required to buffer the external reference. For the reference input

capacitance (C REF IN) and reference output capacitance (C REF

OUT) values, refer to the given external reference IC data sheet

recommendations. As a layout recommendation, the external refer-

ence chip must be placed as close as possible to the AD4083

and its REFIN pin to minimize the series impedance of the track

connecting the REFIN pin to the external reference output. It is

recommended to minimize the exposure of this track to noisy

signals, especially digital ones.

REFERENCE

BUFFER

IN+

IN–

SAR ADC

REFIN

220nF

9.4µF

REFGND

GND

OUT

GND

AD4083

EXTERNAL IC

VOLTAGE REFERENCE

VREF

REFVDD

REFOUT

CREFIN

CREFOUT

Figure 46. AD4083 General External Reference Design Functional Diagram

DATA INTERFACE CLOCKING SOLUTION

When designing the LVDS data interface (see the LVDS Data Inter-

face section), the user must ensure the clocking solution adheres

to the timing specifications of the AD4083 (see Table 2). When

configured for LVDS mode data interface, the user must ensure

that timing specifications stay within the maximum conversion to

clock alignment time of ±535ps (tCCA). In addition, ensure that

a low jitter conversion (CNV) clock is provided such that there

is no unwanted impact to SNR performance. This jitter is signal

frequency dependent; therefore, the level of jitter tolerable in a

given system is dependent on the application use case. The Analog

Devices technical article Maximum SNR vs Clock Jitter provides

further guidance on this topic.

For example, a recommended clocking solution for where the

AD4083 is configured to use the LVDS data interface with a single

lane enabled and using echo clock mode. In this example, a 25MHz

oscillator is selected with low phase noise and jitter. The MT-008

tutorial serves as an aid to convert between phase noise and

RMS phase jitter, often quoted interchangeably in crystal oscillator

product data sheets. The ADF4350 wideband synthesizer with an

integrated voltage-controlled oscillator (VCO) serves as versatile

means of generating a 320MHz clock system clock, while maintain-

ing low jitter and offering flexibility and control to reconfigure this

frequency depending on the application needs. This clock then

feeds the AD9508 clock fanout buffer with output dividers that can

be configured for the desired LVDS level signaling. In the example

shown in Figure 47, one output channel is set to divide by 1 to

output the LVDS clock, while another output channel is configured

to divide by 8 to output the AD4083 conversion clock. This 1:8 ratio

of CNV:CLK frequencies ensures 16 bits of data can be read out

in on the double data rate (DDR), single lane, LVDS data interface.

For a dual lane configuration, such as shown in Figure 48, this ratio

is adjust to 1:4.

The example shows that echo clock mode is used and aids data

alignment for the host controller (in the case a field-programmable

gate array (FPGA)). In self clock mode, where DCO+ and DCO−

AD4083 Datasheet(PDF) 29 Page - Analog Devices

AD4083 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL