13

LT5524

5524f

In fixed gain applications, the LT5524 can be set to 3dB

attenuation relative to maximum gain. As shown in the

Typical Performance Characteristics, this gives a 2dB

reduction in the output noise floor with no loss of linearity.

In general, the output noise floor can be reduced by

decreasing ROUT (and hence power gain), at the cost of

reduced OIP3.

LT5524 Characterization

The LT5524’s typical performance data are based on the

test circuits shown in Figures 9 and 10. Figure 9 does not

necessarily reflect the use of the LT5524 in an actual

application. (For that, see the Application Boards section.)

Rather, it represents a compromise that most accurately

measures the actual operation of the part by itself,

undistorted by the artifacts of the impedance transformation

network, or by external bandwidth limiting factors. Balun

transformers are used to interface with single-ended test

equipment. Input and output resistive attenuators (not

shown) provide broadband I/O impedance control. The

L1, L2 inductors are selected for maximally flat AC output

response. COUT (normally open) shows the placement of

capacitive loading when this is specified as a

characterization variable. The VCCO monitor pin allows

setting the output DC level (5V typical) by adjusting

voltage VOSUP.

APPLICATIO S I FOR ATIO

–

+

T1

1:1

T1

1:1

C7

47nF

DUT

LT5524

ROUT

VCCO

MONITOR

IN+

IN–

C2

0.1µF

C1

0.33µF

C8

47nF

ETC-1-

1-13

PGA0 PGA1 PGA2 PGA3

RSRC

50Ω

R9

35.7Ω

R10

35.7Ω

R7

35.7Ω

R8

35.7Ω

R5

51k

R6

51k

COUT

(OPT)

COUT

(OPT)

VSRC

VCC

L1

(OPT)

R3

37.4Ω

R1

25Ω

R2

25Ω

RLOAD

50Ω

R4

37.4Ω

C4

0.1µF

C5

47nF

C6

47nF

L2

(OPT)

C3

4.7µF

5524 F09

VOSUP

ETC-1-

1-13

ATT =

7.7dB

ROUT

100Ω

200Ω

R3, R4

37.4Ω

87.4Ω

ATT

9dB

12dB

L1, L2

0Ω

33nH

Figure 9. Characterization Board (Simplified Schematic)

C1

0.47µF

J1

0Ω

T1

1:2

IF

IN

T2

4:1

•

•

•

C2

0.1µF

ROUT

100Ω

RLOAD

50Ω

5524 F10

VOSUP

TC2-1T

TC4-1W

J2

0Ω

TRANSFORMER DEMO BOARD

RMATCH

255Ω

EN

VCC1

GND

GND

IN+

IN–

GND

GND

PGA0

PGA1

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

NC

VCC2

GND

GND

OUT–

OUT+

GND

GND

PGA3

PGA2

C3

4.7µF

IF

OUT

C4

0.1µF

LT5524

PGA1

EN

NC

VCC

PGA0

PGA2 PGA3

Figure 10. Output Transformer Application Board (Simplified Schematic)