AD5422 datasheet(19/29 Pages) AD

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Preliminary Technical Data

AD5420

Rev. PrD | Page 19 of 29

Table 7. Input Shift Register Format

MSB

LSB

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

ADDRESS WORD

DATA WORD

Table 8. Control Word Functions

Address

Word

Function

00000000

No Operation (NOP)

00000001

DATA Register

00000010

Readback register value as per Read Address

(See Table 10)

01010101

CONTROL Register

01010110

RESET Register

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can only be

used if LATCH is taken high after the correct number of data

bits have been clocked in. In gated clock mode, a burst clock

containing the exact number of clock cycles must be used, and

LATCH must be taken high after the final clock to latch the

data. The first rising edge of SCLK that clocks in the MSB of the

dataword marks the beginning ot the write cycle. Exactly 24

rising clock edges must be applied to SCLK before LATCH is

brought high. If LATCH is brought high before the 24th rising

SCLK edge, the data written will be invalid. If more than 24

rising SCLK edges are applied before LATCH is brought high,

the input data will also be invalid.

CONTROLLER

DATA IN

LATCH

SDIN

SCLK

DATA OUT

SERIAL CLOCK

CONTROL OUT

SDO

LATCH

SCLK

SDO

LATCH

SCLK

SDO

SDIN

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5420*

Figure 35. Daisy Chaining the AD5420

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