MAX98374 datasheet(52/129 Pages) AD

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I2C Serial Interface

The I2C serial control interface is activated when the

device detects a valid I2C start condition at the SDA

and SCL pins. To detect a valid start condition, the initial

power-up of both supplies must have occurred and the

device cannot currently be in hardware shutdown.

I2C Slave Address

The slave address is defined as the seven most signifi-

cant bits (MSBs) followed by the read/write bit. The seven

MSBs are programmable through the ADDR connection,

and the required SDA and SCL connections for each

address are shown in Table 7. The ADDR pin cannot

be left unconnected (the device may not communicate).

Setting the read/write bit to 1 configures the device for

read mode. Setting the read/write bit to 0 configures the

device for write mode. The I2C slave address is the first

byte of information sent to the device after the START

condition.

I2C Slave Interface Operation

The device features an I2C/SMBus™-compatible, 2-wire

slave serial interface consisting of a serial data line (SDA)

and a serial clock line (SCL). SDA and SCL facilitate com-

munication between the device and the master at clock

rates up to 1MHz (FM+ standard).

Figure 10 shows the 2-wire I2C slave interface timing

diagram. The master generates SCL and initiates data

transfer on the bus. The master device writes data to

the device by transmitting the proper slave address fol-

lowed by two register address bytes (most significant byte

first) and then the data word. Each transmit sequence is

framed by a START (S) or REPEATED START (Sr) condi-

tion and a STOP (P) condition. Each word transmitted to

the device is 8 bits long and is followed by an acknowl-

edge clock pulse.

A master reading data from the device transmits the

proper slave address followed by a series of nine SCL

pulses. The device transmits data on SDA in sync with

the master-generated SCL pulses. The master acknowl-

edges receipt of each byte of data. Each read sequence

is framed by a START (S) or REPEATED START (Sr)

condition, a not acknowledge, and a STOP (P) condition.

SDA operates as both an input and an open-drain output.

A pullup resistor, typically greater than 500Ω, is required

on SDA. SCL operates only as an input. A pullup resistor,

typically greater than 500Ω, is required on SCL if there are

multiple masters on the bus, or if the single master has an

open-drain SCL output. Series resistors in line with SDA

and SCL are optional. Series resistors protect the digital

inputs of the device from high voltage spikes on the bus

lines and minimize crosstalk and undershoot of the bus

signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The

data on SDA must remain stable during the high period

of the SCL pulse. Changes in SDA while SCL is high are

control signals (see the START and STOP Conditions

section).

Table 7. Configuring the I2C Slave Address

ADDR CONNECTION

I2C SLAVE ADDRESS

Connected to DVDD

0x62

Connected to DGND

0x64

Connected to SDA

0x66

Connected to SCL

0x68

MAX98374

Digital Input Class D Speaker Amplifier with DHT

www.maximintegrated.com

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MAX98374 Datasheet(PDF) 52 Page - Analog Devices

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