MAX98374 datasheet(72/129 Pages) AD

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Interrupts

The device supports individually enabled status interrupts

for sending feedback to the host about events that have

occurred on-chip. When enabled, interrupts are transmit-

ted on the IRQ output in I2C control mode and through the

SoundWire slave interface in SoundWire control mode.

Interrupt Bit Field Composition

Each interrupt source has five individual bit field compo-

nents. The function of each component is detailed below

and the corresponding bit fields for each source can be

identified by the appended suffix (shown in parentheses).

Raw Status (RAW)

Each interrupt source has a read-only bit to indicate the

real-time raw status of the interrupt source.

State (STATE)

Each interrupt source has a read-only state bit that is set

whenever a rising edge occurs on the associated raw

status bit. The state bit is set regardless of the setting of

the source enable bit.

Flag (FLAG)

Each interrupt source has a read-only flag bit. If the source

enable bit is set, then the flag bit is set, and an interrupt can

be generated whenever the source state bit is set.

Enable (EN)

Each interrupt source has a dynamic read/write enable

bit. When the enable bit is set, the associated flag bit

is set, and an interrupt can be generated whenever the

source state bit is set.

Clear (CLR)

Each interrupt source has a dynamic write-only clear bit.

Writing a 1 to a clear bit resets the associated state and flag

bits to 0. Writing a 0 to a clear bit has no effect. In I2C con-

trol mode, the IRQ output is deasserted if all flag bits are 0.

IRQ Output Configuration

The device allows the user to configure the drive mode

and polarity of the IRQ output. The IRQ_MODE bit con-

trols the drive mode. If IRQ_MODE is 0, the pin is config-

ured as an open-drained output and requires an external

pullup resistor. If IRQ_MODE is 1, then IRQ is configured

as a push-pull CMOS output.

The IRQ_POL bit controls the polarity of the IRQ bus.

Interrupt events (a flag bit is set high) assert the IRQ bus

low if IRQ_POL = 0 and high if IRQ_POL = 1. The IRQ bus

deasserts if all flag bits are cleared (set low).

Interrupt Sources

The events in Device Interrupt Sources can cause device

interrupts when enabled (corresponding interrupt enable

set high).

IRQ Bus Configuration

DESCRIPTION

BIT PoR

BIT NAME

TYPE

RES

RESERVED

—

Unused

Returns 0 if read.

IRQ_MODE

RW-R

IRQ

IRQ Mode

Controls the drive mode of the IRQ Output.

0 = Open-drain output (an external pullup resistor is necessary)

1 = CMOS push-pull output

IRQ_POL

RW-R

IRQ

IRQ Polarity

Controls the IRQ bus polarity.

0 = Low when any interrupt FLAG bits are high

1 = High when any interrupt FLAG bits are high

IRQ_EN

RW-D

—

IRQ Enable

Enables the IRQ Output.

0 = IRQ output is disabled and is high-impedance

1 = IRQ output is enabled and is controlled by the interrupt controller

MAX98374

Digital Input Class D Speaker Amplifier with DHT

www.maximintegrated.com

Maxim Integrated │ 72

MAX98374 Datasheet(PDF) 72 Page - Analog Devices

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