MAX98374 datasheet(86/129 Pages) AD

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Clock Monitor

The device provides an optional clock monitor that is

enabled by setting CMON_EN (Device Auto-Restart

Configuration) to 1. When enabled, the block monitors

the active clock source (BCLK in I2C control/PCM inter-

face mode and SWCLK in SoundWire control mode) and

automatically places the device into shutdown if a clock

source error is detected. This prevents unwanted signals

from reaching the speaker path output during a fault con-

dition.

The clock monitor detects a clock source error if the

monitored clock source (BCLK or SWCLK) stops high

or low for more than 60μs (typ). The timeout of the clock

monitor is determined by an internal oscillator, which has

a typical variability of ±10% over the devices operating

temperature range.

The clock monitor can be programmed to respond to the

loss and reapplication of the clock source in two ways.

When the CMON_AUTORESTART_EN bit (Device Auto-

Restart Configuration) is set to 0 and a clock source error

is detected, the clock monitor generates an interrupt

(CLKSTOP_*) and places the device into software shut-

down by setting EN to 0. When a valid clock is reapplied,

the clock monitor generates an interrupt (CLKSTART_*);

however, the device remains in software shutdown until

the host sets EN to 1.

When the CMON_AUTORESTART_EN bit is set to 1 and

a clock source error is detected, the clock monitor gener-

ates an interrupt (CLKSTOP_*) and places the device

into shutdown internally. When a valid clock is reapplied,

the clock monitor generates an interrupt (CLKSTART_*)

and the device automatically exits shutdown. The value

of EN is not changed in auto restart mode, and remains

1 throughout the process. As a result, when auto restart

is enabled, the device does not go through the full power-

down/up sequence, and audible glitches may occur.

Clock Monitor in SoundWire Control Mode

If the SoundWire master uses ClockStop events, then

the clock monitor should be disabled in SoundWire con-

trol mode. In this case, to prevent audible glitches, the

SoundWire master should instead place the device into

software shutdown directly prior to initiating a ClockStop

event.

Measurement ADC PVDD Channel Enable

DESCRIPTION

BIT

PoR

BIT NAME

TYPE

RES

RESERVED

—

Unused

Returns 0 if read.

MEAS_ADC_PVDD_EN

RW-D

—

Measurement ADC PVDD Channel Enable

Manually enables the measurement ADC PVDD channel.

0 = PVDD channel disabled

1 = PVDD channel enabled

MAX98374

Digital Input Class D Speaker Amplifier with DHT

www.maximintegrated.com

Maxim Integrated │ 86

MAX98374 Datasheet(PDF) 86 Page - Analog Devices

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