MAX98396 datasheet(49/172 Pages) AD

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PCM Interface Timing

Figure 8 and Figure 9 shows timing for BCLK, LRCLK, DIN, and DOUT. See the Electrical Characteristics table for more

details.

DC x tBCLK

LRCLK

(INPUT)

DIN

(INPUT)

tSYNCSET

tSETUP

tHOLD

tBCLK

BCLK

(INPUT)

LRCLK

(INPUT)

DIN

(INPUT)

tSYNCHOLD

tSETUP

tHOLD

(1-DC) x tBCLK

tSYNCHOLD

BCLK

(INPUT)

(1-DC) x tBCLK

tBCLK

DC x tBCLK

tSYNCSET

BCLK RISING ACTIVE EDGE

BCLK FALLING ACTIVE EDGE

Figure 8. PCM Interface Timing/Slave Mode—LRCLK, BCLK, DIN Timing Diagram

BCLK

tACTV

DOUT

(OUTPUT)

tCLKTX

tHi-Z

Hi-Z

ACTIVE

Hi-Z

Figure 9. PCM Interface Timing/DOUT Timing Diagram

Interrupts

The device supports individually enabled status interrupts for sending feedback to the host about events that have

occurred on-chip. When enabled, interrupts are transmitted on the IRQ output.

Interrupt Bit Field Composition

Each interrupt source has five individual bit field components. The function of each component is detailed as follows, and

the corresponding bit fields for each source can be identified by the appended suffix (shown in parentheses).

● Raw Status (RAW): Each interrupt source has a read-only bit to indicate the real-time raw status of the interrupt

source.

● State (STATE): Each interrupt source has a read-only state bit that is set whenever a rising edge occurs on the

associated raw status bit. The state bit is set regardless of the setting of the source enable bit.

● Flag (FLAG): Each interrupt source has a read-only flag bit. If the source enable bit is set, then the flag bit is set and

an interrupt can be generated whenever the source state bit is set.

● Enable (EN): Each interrupt source has a dynamic read/write enable bit. When the enable bit is set, the associated

flag bit is set and an interrupt can be generated whenever the source state bit is set.

● Clear (CLR): Each interrupt source has a dynamic write-only clear bit. Writing a 1 to a clear bit resets the associated

state and flag bits to 0. Writing a 0 to a clear bit has no effect. In I2C control mode, the IRQ output is deasserted if all

flag bits are 0.

MAX98396

20V Digital Input Class-DG Amplifier with I/V

Sense and Brownout Prevention

www.maximintegrated.com

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