ADPL21610ECPZ datasheet(8/15 Pages) AD

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The decision to use either low ESR (ceramic) capaci-

tors or the higher ESR (tantalum or OS-CON) capaci-

tors can affect the stability of the overall system. The

ESR of any capacitor, along with the capacitance itself,

contributes a zero to the system. For the tantalum and

OS-CON capacitors, this zero is located at a lower

frequency due to the higher value of the ESR, while

the zero of a ceramic capacitor is at a much higher

frequency and can generally be ignored.

A phase lead zero can be intentionally introduced by

placing a capacitor (C4) in parallel with the resistor

(R1) between VOUT and VFB as shown in Figure 1. The

frequency of the zero is determined by the following

equation.

fZ =

2� x R1 x C4

By choosing the appropriate values for the resistor

and capacitor, the zero frequency can be designed to

improve the phase margin of the overall converter. The

typical target value for the zero frequency is between

35kHz to 55kHz.

Diode Selection

A Schottky diode is recommended for use with the

ADPL21610. The Philips PMEG 2005 is a very good

choice. Where the switch voltage exceeds 20V, use

the PMEG 3005 (a 30V diode). These diodes are

rated to handle an average forward current of 0.5A.

In applications where the average forward current of

the diode exceeds 0.5A, a Philips PMEG 2010 rated

at 1A is recommended. For higher efficiency, use a

diode with better thermal characteristics such as the

On Semiconductor MBRM120 (a 20V diode) or the

MBRM140 (a 40V diode).

Setting Output Voltage

To set the output voltage, select the values of R1 and

R2 (see Figure 1) according to the following equation.

R1 = R2

VOUT

1.255V

–

A good value for R2 is 13.3kΩ which sets the current

in the resistor divider chain to 1.255V/13.3kΩ = 94µA.

Layout Hints

The high speed operation of the ADPL21610 demands

careful attention to board layout. You will not get adver-

tised performance with careless layout. Figure 11a

shows the recommended component placement for

the ThinSOT package. Figure 11b shows the recom-

mended component placement for the DFN package.

Note the vias under the Exposed Pad. These should

connect to a local ground plane for better thermal per-

formance.

www.analog.com

Analog Devices │ 8

ADPL21610

1.1A Step-Up DC/DC

Converter with Integrated Soft-Start

Figure 11a. Suggested Layout—ThinSOT

Figure 11b. Suggested Layout—DFN

GND

VOUT

VIN

SHDN

CSS

GND

VOUT

CSS

VIN

SHDN

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