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TLC770X Datasheet(PDF) 14 Page - Texas Instruments |
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TLC770X Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 27 page ![]() 14 input IN, then only one transistor will be conducting, and no lateral current flows through the circuit. With input levels that are between the specified High and Low levels, a current flows between the supply voltage VDD and Ground. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 00.5 1 1.5 22.5 33.5 4 4.5 5 voltage at CONTROL-input [V] Figure 11. Dependence of the lateral current at the CONTROL input on the input voltage (VDD=5V) The typical current consumption of a TLC770X is only 10 µA, whereas the lateral current can be about 100x higher. With some applications (see Section 5, Figure 21.) undefined levels may exists at the CONTROL input. In order to prevent the CONTROL input from causing an increase of current consumption, it is inhibited as a result of internal circuitry if the RESET Output − is active; that is, when a Low level is applied to the input RESIN , or the voltage at the SENSE input is below the threshold voltage Vt . In the quiescent state, the input RESIN must be at a High level, and the input CONTROL at Low. With supply voltages of less than the threshold voltage Vt of the MOS transistors ( VV t ≈ 1 ), the device can not operate, and in this situation it is not possible to say what the voltage level at the output will be. Although with this order of voltage no definite function can be expected from the circuit being monitored, this does not mean any restriction in practice. With a supply voltage above 1 V there will be a Low level at the RESET output, provided the input conditions are fulfilled. With a supply voltage of more than 2 V, all parts of the circuit in the TLC770X operate as specified in the Data Sheet. In order that the circuit may recognize voltage reductions at the SENSE input, these voltages must be applied for a certain time period. This time depends on the magnitude of the voltage reductions: the greater these are, the shorter is the time period needed to start the RESET procedure. Figure 12. shows this relationship. |
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