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SM5330AF Datasheet(PDF) 2 Page - Nippon Precision Circuits Inc |
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SM5330AF Datasheet(HTML) 2 Page - Nippon Precision Circuits Inc |
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2 / 22 page  SM5330A SEIKO NPC CORPORATION —2 BLOCK DIAGRAM SCL SDA VDD DGND OUT_1 I C BUS I/F 2 IN1_L1 Control Logic IN1_L2 IN1_L3 IN1_SW Bias /off Bias /off Clamp /Bias /off Comparator VCCD ADS I/O_1 I/O_0 Reference IN1_1 IN1_2 IN1_3 IN2_L1 IN2_L2 IN2_L3 IN2_SW Bias /off Bias /off Clamp /Bias /off IN2_1 IN2_2 IN2_3 Bias /off Bias /off Clamp /Bias /off IN3_1 IN3_2 IN3_3 Bias /off Bias /off Clamp /Bias /off IN4_1 IN4_2 IN4_3 5th order LPF CH-3 6dB 5th order LPF CH-2 6dB 5th order LPF CH-1 6dB DAC DAC 0dB VCC DAC_1 DAC_0 OUT_2 OUT_3 GND YOUT VREF IREF TEST |
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