6300ESB datasheet(13/848 Pages) INTEL

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Intel® 6300ESB I/O Controller Hub

November 2007

Order Number: 300641-004US

Contents—Intel® 6300ESB ICH

5.17.5.3 Packet Field Formats ............................................................... 208

5.17.5.4 Address Fields ........................................................................ 210

5.17.5.5 Frame Number Field ................................................................ 211

5.17.5.6 Data Field .............................................................................. 211

5.17.5.7 Cyclic Redundancy Check (CRC)................................................ 211

5.17.6 Packet Formats .................................................................................... 211

5.17.6.1 Token Packets ........................................................................ 211

5.17.6.2 Start of Frame Packets ............................................................ 212

5.17.6.3 Data Packets .......................................................................... 212

5.17.6.4 Handshake Packets ................................................................. 213

5.17.6.5 Handshake Responses ............................................................. 213

5.17.7 USB Interrupts..................................................................................... 214

5.17.7.1 Overview ............................................................................... 214

5.17.7.2 Transaction Based Interrupts.................................................... 214

5.17.7.3 Non-Transaction Based Interrupts ............................................. 216

5.17.8 USB Power Management ....................................................................... 216

5.17.9 USB Legacy Keyboard Operation ............................................................ 217

5.18 USB EHCI Controller (D29:F7)........................................................................... 221

5.18.1 Overview ............................................................................................ 221

5.18.2 EHC Initialization.................................................................................. 221

5.18.2.1 Power On............................................................................... 222

5.18.2.2 BIOS Initialization ................................................................... 222

5.18.2.3 Driver Initialization ................................................................. 222

5.18.2.4 EHC Resets ............................................................................ 222

5.18.3 Data Structures in Main Memory............................................................. 223

5.18.4 USB 2.0 Enhanced Host Controller DMA................................................... 224

5.18.4.1 Periodic List Execution ............................................................. 224

5.18.4.2 Asynchronous List Execution .................................................... 226

5.18.5 Data Encoding and Bit Stuffing ............................................................... 227

5.18.6 Packet Formats .................................................................................... 227

5.18.7 USB EHCI Interrupts and Error Conditions ............................................... 227

5.18.7.1 Aborts on USB EHCI-Initiated Memory Reads.............................. 228

5.18.8 USB EHCI Power Management................................................................ 228

5.18.8.1 Pause Feature ........................................................................ 228

5.18.8.2 Suspend Feature..................................................................... 229

5.18.8.3 ACPI Device States ................................................................. 229

5.18.8.4 ACPI System States ................................................................ 229

5.18.8.5 Low-power system Considerations............................................. 229

5.18.9 Interaction with Classic Host Controllers .................................................. 230

5.18.9.1 Port-Routing Logic .................................................................. 230

5.18.9.2 Device Connects ..................................................................... 231

5.18.9.3 Device Disconnects ................................................................. 231

5.18.9.4 Effect of Resets on Port-Routing Logic........................................ 232

5.18.10USB 2.0 Legacy Keyboard Operation ....................................................... 232

5.18.11USB 2.0 EHCI Based Debug Port............................................................. 232

5.18.11.1Overview ............................................................................... 233

5.18.11.2Theory of Operation ................................................................ 233

5.19 SMBus Controller Functional Description (D31:F3) ............................................... 237

5.19.1 Overview ............................................................................................ 237

5.19.2 Host Controller..................................................................................... 238

5.19.2.1 Command Protocols ................................................................ 239

5.19.2.2 I2C Behavior .......................................................................... 249

5.19.2.3 Heartbeat for Use with the External LAN Controller...................... 249

5.19.3 Bus Arbitration..................................................................................... 249

5.19.4 Bus Timing .......................................................................................... 249

5.19.4.1 Clock Stretching ..................................................................... 249

5.19.4.2 Bus Time Out (Intel® 6300ESB ICH as SMBus Master) ................. 250

6300ESB Datasheet(PDF) 13 Page - Intel Corporation

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