6300ESB datasheet(18/848 Pages) INTEL

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Intel® 6300ESB ICH—Contents

Intel® 6300ESB I/O Controller Hub

November 2007

Order Number: 300641-004US

8.7.4

COPROC_ERR—Coprocessor Error Register............................................... 383

8.7.5

RST_CNT—Reset Control Register ........................................................... 383

8.8

Power Management Registers (D31:F0) .............................................................. 384

8.8.1

Power Management PCI Configuration Registers (D31:F0) .......................... 384

8.8.1.1

Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) ......................................................................... 385

8.8.1.2

Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) ......................................................................... 386

8.8.1.3

Offset A4h: GEN_PMCON_3—General PM Configuration 3

8.8.1.4

Offset ACh: RST_CNT2—Reset Control 2 Register (PM—D31:F0) .... 388

8.8.1.5

Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register

(PM—D31:F0) ......................................................................... 389

8.8.1.6

Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register

(PM—D31:F0) ......................................................................... 390

8.8.1.7

Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7]

Trap Range Register for Devices 4-7 (PM—D31:F0)...................... 390

8.8.1.8

Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register

for Devices 4-7 (PM—D31:F0) ................................................... 391

8.8.2

APM I/O Decode ................................................................................... 392

8.8.2.1

APM_CNT—Advanced Power Management Control Port Register ..... 392

8.8.2.2

APM_STS—Advanced Power Management Status Port Register ...... 392

8.8.3

Power Management I/O Registers ........................................................... 393

8.8.3.1

PM1_STS—Power Management 1 Status Register......................... 394

8.8.3.2

PM1_EN—Power Management 1 Enable Register .......................... 396

8.8.3.3

PM1_CNT—Power Management 1 Control.................................... 397

8.8.3.4

PM1_TMR—Power Management 1 Timer Register ......................... 398

8.8.3.5

PROC_CNT—Processor Control Register ...................................... 398

8.8.3.6

LV2—Level 2 Register .............................................................. 400

8.8.3.7

GPE0_STS—General Purpose Event 0 Status Register................... 400

8.8.3.8

GPE0_EN—General Purpose Event 0 Enables Register................... 404

8.8.3.9

SMI_EN—SMI Control and Enable Register.................................. 405

8.8.3.10 SMI_STS—SMI Status Register.................................................. 407

8.8.3.11 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register ................... 410

8.8.3.12 ALT_GP_SMI_STS—Alternate GPI SMI Status Register.................. 411

8.8.3.13 MON_SMI—Device Monitor SMI Status and Enable Register........... 411

8.8.3.14 DEVACT_STS—Device Activity Status Register............................. 412

8.8.3.15 DEVTRAP_EN— Device Trap Enable Register ............................... 414

8.8.3.16 BUS_ADDR_TRACK— Bus Address Tracker.................................. 415

8.8.3.17 BUS_CYC_TRACK— Bus Cycle Tracker........................................ 415

8.9

System Management TCO Registers (D31:F0)...................................................... 416

8.9.1

TCO Register I/O Map............................................................................ 416

8.9.2

TCO1_RLD—TCO Timer Reload and Current Value ..................................... 417

8.9.3

TCO1_TMR—TCO Timer Initial Value........................................................ 417

8.9.4

TCO1_DAT_IN—TCO Data In Register...................................................... 418

8.9.5

TCO1_DAT_OUT—TCO Data Out Register ................................................. 418

8.9.6

TCO1_STS—TCO1 Status Register........................................................... 419

8.9.7

TCO2_STS—TCO2 Status Register........................................................... 421

8.9.8

TCO1_CNT—TCO1 Control Register ......................................................... 422

8.9.9

TCO2_CNT—TCO2 Control Register ......................................................... 423

8.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................... 423

8.9.11 Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Register .............. 424

8.9.12 Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation Register... 424

8.10 General Purpose I/O Registers (D31:F0) ............................................................. 425

8.10.1 GPIO Register I/O Address Map .............................................................. 425

8.10.2 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register ........... 426

8.10.3 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select Register .... 426

6300ESB Datasheet(PDF) 18 Page - Intel Corporation

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