6300ESB datasheet(14/848 Pages) INTEL

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Intel® 6300ESB ICH—Contents

Intel® 6300ESB I/O Controller Hub

November 2007

Order Number: 300641-004US

5.19.5 Interrupts/SMI# ................................................................................... 250

5.19.6 SMBALERT#......................................................................................... 251

5.19.7 SMBus CRC Generation and Checking ...................................................... 251

5.19.8 SMBus Slave Interface........................................................................... 251

5.19.8.1 Format of Slave Write Cycle...................................................... 252

5.19.8.2 Format of Read Command ........................................................ 254

5.19.8.3 Format of Host Notify Command................................................ 256

5.20 AC’97 Controller Functional Description (Audio D31:F5, Modem D31:F6) ................. 257

5.20.1 Overview ............................................................................................. 257

5.20.1.1 PCI Power Management ........................................................... 260

5.20.2 AC-Link Overview ................................................................................. 260

5.20.2.1 AC-link Output Frame (SDOUT) ................................................. 263

5.20.2.2 Output Slot 0: Tag Phase ......................................................... 263

5.20.2.3 Output Slot 1: Command Address Port ....................................... 264

5.20.2.4 Output Slot 2: Command Data Port ........................................... 264

5.20.2.5 Output Slot 3: PCM Playback Left Channel .................................. 264

5.20.2.6 Output Slot 4: PCM Playback Right Channel ................................ 264

5.20.2.7 Output Slot 5: Modem Codec .................................................... 264

5.20.2.8 Output Slot 6: PCM Playback Center Front Channel ...................... 265

5.20.2.9 Output Slots 7-8: PCM Playback Left and Right Rear Channels ....... 265

5.20.2.10Output Slot 9: Playback Sub Woofer Channel .............................. 265

5.20.2.11Output Slots 10-11: Reserved ................................................... 265

5.20.2.12Output Slot 12: I/O Control ...................................................... 265

5.20.2.13AC-Link Input Frame (SDIN) ..................................................... 265

5.20.2.14Input Slot 0: Tag Phase ........................................................... 267

5.20.2.15Input Slot 1: Status Address Port/Slot Request Bits ..................... 267

5.20.2.16Input Slot 2: Status Data Port................................................... 268

5.20.2.17Input Slot 3: PCM Record Left Channel ....................................... 268

5.20.2.18Input Slot 4: PCM Record Right Channel ..................................... 268

5.20.2.19Input Slot 5: Modem Line ......................................................... 268

5.20.2.20Input Slot 6: Optional Dedicated Microphone Record Data............. 268

5.20.2.21Input Slots 7-11: Reserved....................................................... 268

5.20.2.22Input Slot 12: I/O Status ......................................................... 268

5.20.2.23Register Access....................................................................... 269

5.20.3 AC-Link Low Power Mode ....................................................................... 270

5.20.3.1 External Wake Event................................................................ 270

5.20.4 AC‘97 Cold Reset .................................................................................. 271

5.20.5 AC‘97 Warm Reset ................................................................................ 271

5.20.6 System Reset....................................................................................... 273

5.20.7 Hardware Assist to Determine AC_SDIN Used Per Codec ............................ 273

5.20.8 Software Mapping of AC_SDIN to DMA Engine .......................................... 274

6.1

PCI Devices and Functions ................................................................................ 275

6.2

PCI Configuration Map ...................................................................................... 277

6.3

I/O Map.......................................................................................................... 278

6.3.1

Fixed I/O Address Ranges ...................................................................... 278

6.3.2

Variable I/O Decode Ranges................................................................... 281

6.4

Memory Map ................................................................................................... 283

6.4.1

Boot-Block Update Scheme .................................................................... 285

Hub Interface to PCI Bridge Registers (D30:F0)..................................................... 287

7.1

PCI Configuration Registers (D30:F0) ................................................................. 287

7.1.1

Offset 00 - 01h: VID—Vendor ID Register (HUB-PCI—D30:F0).................... 288

7.1.2

Offset 02 - 03h: DID—Device ID Register (HUB-PCI—D30:F0) .................... 288

7.1.3

Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0)................... 289

7.1.4

Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—D30:F0) ..

290

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