6300ESB datasheet(39/848 Pages) INTEL

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Intel® 6300ESB I/O Controller Hub

November 2007

Order Number: 300641-004US

Contents—Intel® 6300ESB ICH

324 Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F1) ....................................... 436

325 Offset 04h - 05h: CMD—Command Register (IDE—D31:F1) ......................................... 437

326 Offset 06 - 07h: STS—Device Status Register (IDE—D31:F1)....................................... 438

327 Offset 08h: RID—Revision ID Register (IDE—D31:F1) ................................................. 439

328 Offset 09h: PI—Programming Interface (IDE—D31:F1) ............................................... 439

329 Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1) ....................................................... 440

330 Offset 0Bh: BCC—Base Class Code (IDE—D31:F1)...................................................... 441

331 Offset 0Dh: MLT—Master Latency Timer (IDE—D31:F1) .............................................. 441

332 Offset 10h - 13h: PCMD_BAR—Primary Command Block Base Address Register (IDE—D31:F1)

441

333 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) ...

442

334 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base Address Register (IDE

D31:F1)442

335 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) .

443

336 Offset 20h - 23h: BM_BASE—Bus Master Base Address Register (IDE—D31:F1) ............. 443

337 Offset 24h - 27h: CPBA – IDE Command Posting Base Address .................................... 444

338 Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID (IDE—D31:F1) ............................. 445

339 Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—D31:F1)........................................... 446

340 Offset 3Ch: INTR_LN—Interrupt Line Register (IDE—D31:F1) ...................................... 446

341 Offset 3Dh: INTR_PN—Interrupt Pin Register (IDE—D31:F1)........................................ 447

342 IDE_TIM—IDE Timing Register (IDE—D31:F1) ........................................................... 448

343 Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE Timing Register (IDE—D31:F1) ............... 451

344 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1) .................. 452

345 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1) ............ 453

346 IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)....................................... 455

347 Bus Master IDE I/O Registers .................................................................................. 455

348 BMIC[P,S]—Bus Master IDE Command Register ......................................................... 456

349 BMIS[P,S]—Bus Master IDE Status Register............................................................... 457

350 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register ...................................... 459

351 PCI Configuration Map (USB—D29:F0/F1) ................................................................. 461

352 Offset 00 - 01h: VID—Vendor Identification Register (USB—D29:F0/F1) ........................ 462

353 Offset 02 - 03h: DID—Device Identification Register (USB—D29:F0/F1) ........................ 462

354 Offset 04 - 05h: CMD—Command Register (USB—D29:F0/F1)...................................... 463

355 Offset 06 - 07h: STA—Device Status Register (USB—D29:F0/F1) ................................. 464

356 Offset 08h: RID—Revision Identification Register (USB—D29:F0/F1)............................. 464

357 Offset 09h: PI—Programming Interface (USB—D29:F0/F1) .......................................... 465

358 Offset 0Ah: SCC—Sub Class Code Register (USB—D29:F0/F1) ..................................... 465

359 Offset 0Bh: BCC—Base Class Code Register (USB—D29:F0/F1) .................................... 465

360 Offset 0Dh: MLT—Master Latency Timer .................................................................... 466

361 Offset 0Eh: HTYPE—Header Type Register (USB—D29:F0/F1) ...................................... 466

362 Offset 20 - 23h: BASE—Base Address Register (USB—D29:F0/F1) ................................ 467

363 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (USB—D29:F0/F1).............................. 467

364 Offset 2Eh-2Fh: SID—Subsystem ID (USB—D29:F0/F1) .............................................. 468

365 Offset 3Ch: INTR_LN—Interrupt Line Register (USB—D29:F0/F1) ................................. 468

366 Offset 3Dh: INTR_PN—Interrupt Pin Register (USB—D29:F0/F1) .................................. 469

367 Offset 60h: USB_RELNUM—USB Release Number Register (USB—D29:F0/F1) ................ 469

368 Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control Register (USB—D29:F0/

F1)470

369 Offset C4h: USB_RES—USB Resume Enable Register (USB—D29:F0/F1) ....................... 472

370 USB I/O Registers .................................................................................................. 473

371 Offset 00 - 01h: USBCMD—USB Command Register.................................................... 474

372 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation ................. 477

373 Offset 02 - 03h: USBSTA—USB Status Register .......................................................... 478

6300ESB Datasheet(PDF) 39 Page - Intel Corporation

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