6300ESB datasheet(45/848 Pages) INTEL

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Intel® 6300ESB I/O Controller Hub

November 2007

Order Number: 300641-004US

Contents—Intel® 6300ESB ICH

646 Line Status Register (LSR) ...................................................................................... 718

647 Modem Control Register (MCR) ................................................................................ 720

648 Modem Status Register (MSR) ................................................................................. 721

649 Scratch Pad Register (SCR) ..................................................................................... 722

650 Divisor Latch Register Low (DLL).............................................................................. 722

651 Divisor Latch Register High (DLH) ............................................................................ 723

652 Scratch Pad Register P60 (SCR60)............................................................................ 725

653 Scratch Pad Register P64 (SCR64)............................................................................ 725

654 SIU_SERIRQ Sampling Periods................................................................................. 727

655 Configuration Registers Summary ............................................................................ 730

656 Global Control Registers.......................................................................................... 731

657 Logical Device 4 (Serial Port 0) ................................................................................ 732

658 Logical Device 5 (Serial Port 1) ................................................................................ 734

659 Logical Device 7 (Port Emulation) ............................................................................. 735

660 PCI Configuration Map (SATA–D31:F2) ..................................................................... 737

661 Offset 00 - 01h: VID—Vendor ID Register (SATA—D31:F2).......................................... 738

662 Offset 02 - 03h: DID—Device ID Register (SATA—D31:F2) .......................................... 739

663 Offset 04h - 05h: CMD—Command Register (SATA–D31:F2)........................................ 739

664 Offset 06 - 07h: STS—Device Status Register (SATA–D31:F2) ..................................... 741

665 Offset 09h: PI—Programming Interface (SATA–D31:F2) .............................................. 742

666 Offset 0Ah: SCC—Sub Class Code (SATA–D31:F2)...................................................... 742

667 Offset 0Bh: BCC—Base Class Code (SATA–D31:F2) .................................................... 743

668 Offset 0Dh: MLT—Master Latency Timer (SATA–D31:F2) ............................................. 743

669 Offset 10h - 13h: PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2)

744

670 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2) ..

744

671 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base Address Register (IDE

D31:F1)745

672 Offset 14h - 17h: SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) .

745

673 Offset 20h - 23h: BAR—Legacy Bus Master Base Address Register (SATA–D31:F2) ......... 746

674 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SATA–D31:F2).................................. 746

675 Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2) ................................................ 747

676 Offset 34h: CAP—Capabilities Pointer Register (SATA–D31:F2).................................... 747

677 Offset 3Ch: INTR_LN—Interrupt Line Register (SATA–D31:F2) ..................................... 747

678 Offset 3Dh: INTR_PN—Interrupt Pin Register (SATA–D31:F2) ...................................... 748

679 Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register (SATA–D31:F2) ..................... 748

680 Offset 44h: SIDETIM—Slave IDE Timing Register (SATA–D31:F2)................................. 750

681 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2) ................. 751

682 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2) ........... 752

683 Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2)..................... 754

684 Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA–D31:F2).................. 755

685 Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–D31:F2) ..................... 755

686 Offset 74 - 75h: PMCS—PCI Power Management Control and Status (SATA–D31:F2)....... 756

687 Offset 80 - 81h: MID—Message Signaled Interrupt Identifiers (SATA–D31:F2)................ 757

688 Offset 82 - 83h: MC—Message Signaled Interrupt Message Control (SATA–D31:F2) ........ 757

689 Offset 84 - 87h: MA—Message Signaled Interrupt Message Address (SATA–D31:F2) ....... 758

690 Offset 88 - 89h: MD—Message Signaled Interrupt Message Data (SATA–D31:F2) ........... 759

691 Offset 90h: MAP—Address Map (SATA–D31:F2) ......................................................... 759

692 Offset 92h: PCS—Port Status and Control (SATA–D31:F2) ........................................... 760

693 Offset A0h: SRI—SATA Registers Index (SATA–D31:F2) .............................................. 760

694 Offset A4h - A7h: SRD—SATA Registers Data (SATA–D31:F2)...................................... 761

695 STTT—SATA TX Termination Test Register A (SATA–D31:F2) ....................................... 762

696 STOT — SATA TX Output Test Register (SATA–D31:F2)............................................... 762

6300ESB Datasheet(PDF) 45 Page - Intel Corporation

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