6300ESB datasheet(33/848 Pages) INTEL

33 / 848 page

Intel® 6300ESB I/O Controller Hub

November 2007

Order Number: 300641-004US

Contents—Intel® 6300ESB ICH

Tables

Industry Specifications.............................................................................................. 49

2Intel® 6300ESB ICH Clock Domains............................................................................ 53

Hub Interface Signals ............................................................................................... 55

Firmware Hub Interface Signals ................................................................................. 56

PCI Interface Signals ................................................................................................ 57

PCI-X Interface Signals ............................................................................................. 60

SATA Interface Signals ............................................................................................. 64

IDE Interface Signals................................................................................................ 64

LPC Interface Signals................................................................................................ 66

10 Interrupt Signals...................................................................................................... 66

11 USB Interface Signals ............................................................................................... 67

12 Power Management Interface Signals.......................................................................... 68

13 CPU Interface Signals ............................................................................................... 69

14 SM Bus Interface Signals .......................................................................................... 71

15 System Management Interface Signals........................................................................ 71

16 Real Time Clock Interface.......................................................................................... 71

17 Other Clocks ........................................................................................................... 72

18 Miscellaneous Signals ............................................................................................... 72

19 AC’97 Link Signals.................................................................................................... 73

20 Universal Asynchronous Receive and Transmit (UART0, 1)............................................. 73

21 General Purpose I/O Signals ...................................................................................... 75

22 Power and Ground Signals......................................................................................... 76

23 Functional Strap Definitions ....................................................................................... 77

24 Revision and Device ID Table..................................................................................... 78

25 Intel® 6300ESB I/O Controller Hub Power Planes ......................................................... 79

26 Integrated Pull-Up and Pull-Down Resistors ................................................................. 80

27 IDE Series Termination Resistors................................................................................ 81

28 Power Plane and States for Output and I/O Signal for Desktop Configurations .................. 83

29 Power Plane for Input Signals for Desktop Configurations .............................................. 90

30 Type 0 Configuration Cycle Device Number Translation ................................................. 96

31 LPC Cycle Types Supported ....................................................................................... 98

32 Start Field Bit Definitions .......................................................................................... 98

33 Cycle Type Bit Definitions.......................................................................................... 99

34 Transfer Size Bit Definition ........................................................................................ 99

35 SYNC Bit Definition................................................................................................... 99

36 Response to Sync Failures ....................................................................................... 100

37 Fixed Priority ......................................................................................................... 104

38 DMA Transfer Size.................................................................................................. 105

39 Address Shifting in 16-bit I/O DMA Transfers ............................................................. 105

40 Counter Operating Modes ........................................................................................ 111

41 Interrupt Controller Core Connections ....................................................................... 113

42 Interrupt Status Registers ....................................................................................... 114

43 Content of Interrupt Vector Byte .............................................................................. 115

44 Interrupt Mapping in Non-APIC ................................................................................ 123

45 APIC Interrupt Mapping, APIC0 Agent ....................................................................... 124

46 APIC Interrupt Mapping, APIC1 Agent ....................................................................... 125

47 Arbitration Cycles................................................................................................... 126

48 APIC Message Formats ........................................................................................... 126

49 EOI Message ......................................................................................................... 127

50 Short Message....................................................................................................... 128

51 APIC Bus Status Cycle Definition .............................................................................. 129

52 Lowest Priority Message (Without Focus Processor)..................................................... 130

53 Remote Read Message............................................................................................ 131

6300ESB Datasheet(PDF) 33 Page - Intel Corporation

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