PCA9601DPZ datasheet(15/31 Pages) NXP

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NXP Semiconductors

PCA9601

Dual bidirectional bus buffer

B: The effective stretching of the nominal LOW period of SCL at the master caused by

the buffer and bus rise times. See Figure 17.

C: The propagation delay of the slave's response signal through the buffers and wiring

back to the master. The important delay is that of a rising edge in the SDA signal. Rising

edges are always slower and are therefore delayed by a longer time than falling edges.

(The rising edges are limited by the passive pull-up while falling edges are actively

driven); see Figure 18.

The timing requirement in any I2C-bus system is that a slave's data response (which is

provided in response to a falling edge of SCL) must be received at the master before the

end of the corresponding LOW period of SCL as appears on the bus wiring at the master.

Since all slaves will, as a minimum, satisfy the worst case timing requirements of their

speed class (Fast-mode, Fm+, etc.), they must provide their response, allowing for the

set-up time, within the minimum allowed clock LOW period, e.g., 450 ns (max.) for Fm

+ parts. In systems that introduce additional delays it may be necessary to extend the

minimum clock LOW period to accommodate the ‘effective’ delay of the slave's response.

The effective delay of the slave’s response equals the total delays in SCL falling edge

from the master reaching the slave (Figure 16) minus the effective delay (stretch) of the

SCL rising edge (Figure 17) plus total delays in the slave's response data, carried on

SDA, reaching the master (Figure 18).

The master microcontroller should be programmed to produce a nominal SCL LOW

period as follows:

(1)

The actual LOW period will become (the programmed value + the stretching time B).

When this actual LOW period is then less than the specified minimum, the specified

minimum should be used.

Example 1:

It is required to connect an Fm+ slave, with Rs × Cs product of 100 ns, to a 5 V Fast-

mode system also having 100 ns Rm × Cm using two PCA9601’s to buffer a 5 V bus

with 4 nF loading and 160 Ω pull-up.

Calculate the allowed bus speed:

Delay A = 120 + 85 + (2.5 + [4 × 4]) × 5 + 50 = 347.5 ns

Delay B = 115 + 100 + 70 = 285 ns

Delay C = 115 + 20 + 0.7(100 + 100) = 275 ns

The maximum Fm+ slave response delay must be < 450 ns so the programmed LOW

period is calculated as:

LOW ≥ 450 + 347.5 - 285 + 275 + 100 = 887.5 ns

The actual LOW period will be 887.5 + 285 = 1 173 ns, which is below the Fast-mode

minimum, so the programmed LOW period must be increased to (1300 - 285) = 1015

ns, so the actual LOW equals the 1300 ns requirement and this shows that this Fast-

mode system may be safely run to its limit of 400 kHz.

Example 2:

It is required to buffer a Master with Fm+ speed capability, but only 3 mA sink

capability, to an Fm+ bus. All the system operates at 3.3 V. The Master Rm × Cm

product is 50 ns. Only one PCA9601 is used. The Fm+ bus becomes the buffered

bus. The Fm+ bus has 200 pF loading and 150 Ω pull-up, so its Rb × Cb product is 30

ns. The Fm+ slave has a specified data valid time tVD;DAT maximum of 300 ns.

PCA9601

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 4 January 2022

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