PCF85263ATLSLASHA datasheet(30/92 Pages) NXP

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NXP Semiconductors

PCF85263A

Tiny Real-Time Clock/calendar with alarm function, battery switch-over, time stamp input, and I2C-bus

7.7.1 Timestamps interrupts

The generation of interrupts from the timestamp functions is controlled via the timestamp

interrupt enable bits; TSRIEA and TSRIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The loading of new information into one of the timestamp registers can be used to

generate an interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed

signal every time a timestamp register updates or as a permanently active signal which

follows the condition of timestamp flags, TSR1F to TSR3F. The timestamp flags remain

set until cleared by command.

When enabled, interrupts are triggered every time a timestamp register updates and

even if the associated flag is not cleared, an interrupt pulse can be generated.

See Section 7.9 for interrupt control.

7.8 Offset register

The PCF85263A incorporates an offset register (address 24h) which can be used to

implement several functions, such as:

• Accuracy tuning

• Aging adjustment

• Temperature compensation

Bit

Symbol

Value

Description

7 to 0

OFFSET[7:0]

see Table 24

offset value

Table 22. Offset - offset register (address 24h) bit description

There are two modes which define the correction period, normal mode and fast mode.

The

normal mode is suitable for offset trimming. The fast mode is suitable for dynamic

offset correction e.g. implementing a temperature correction. The fast mode consumes

more current. Offset mode is defined by bit OFFM in the Oscillator register (Section 7.10).

See Section 7.10

Bit

Symbol

Value

Description

offset mode bit

0 [1]

normal mode: correction is made every 4

hours; 2.170 ppm/step

OFFM

fast mode: correction is made once every 8

minutes;2.0345 ppm/step

Table 23. OFFM bit - oscillator control register (address 25h)

[1]

Default value.

For OFFM = 0, each LSB introduces an offset of 2.170 ppm. For OFFM = 1, each LSB

introduces an offset of 2.0345 ppm. The offset value is coded in two’s complement giving

a range of +127 LSB to -128 LSB, see Table 24.

PCF85263A

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Product data sheet

Rev. 5 — 1 February 2021

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PCF85263ATL/A Datasheet(PDF) 30 Page - NXP Semiconductors

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