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PCF85263ATL/A Datasheet(PDF) 58 Page - NXP Semiconductors |
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PCF85263ATL/A Datasheet(HTML) 58 Page - NXP Semiconductors |
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58 / 92 page  NXP Semiconductors PCF85263A Tiny Real-Time Clock/calendar with alarm function, battery switch-over, time stamp input, and I2C-bus aaa-010487 Write ACK from slave S A A A P slave address + 0 write data write data write data A S A A A P read data read data read data A Read ACK from slave ACK from slave ACK from master slave address + 1 ACK from slave ACK from slave ACK from master ACK from slave Figure 34. I2C read and write protocol SCL SDA ACK ACK S P aaa-010489 SCL SDA bit7 bit0 ACK ACK S START condition STOP condition P ACK of 1st byte from slave ACK of 2nd byte from slave I2C read example I2C write example bit7 bit0 1st byte, slave address with R/W = 0 write 2nd byte START condition STOP condition 1st byte, slave address with R/W = 1 ACK of 1st byte from slave ACK of 2nd byte from slave bit7 bit0 bit7 bit0 read 2nd byte Figure 35. I2C read and write signaling 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time are interpreted as STOP or START conditions. 8.2 START and STOP conditions A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 35). 8.3 Acknowledge Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as logic 0. A not-acknowledge is defined as logic 1. PCF85263A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 5 — 1 February 2021 58 / 92 |
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