PCF85263ATLSLASHA datasheet(48/92 Pages) NXP

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NXP Semiconductors

PCF85263A

Tiny Real-Time Clock/calendar with alarm function, battery switch-over, time stamp input, and I2C-bus

In mechanical switch detector mode (TSIM = 1), the TS pin is sampled at a rate of 16 Hz

for a period of 30.5 μs. At the same time as the sample a pull-up resistor is activated to

detect an open pin or a pin shorted to VSS. The input is referenced to the internal power

supply. This mode operates when on VDD or VBAT. The pull-up resistor value can be

controlled by TSPULL bit in the Pin_IO register (see Section 7.12).

7.12.5.1 TS pin input mode

There are two input types which are controlled by the TSIM bit. The TS input can be used

to generate a timestamp event by configuring the timestamp mode bits; TSR2M[2:0] and

TSR1M[1:0] bits in TSR_mode register (see Table 19).

Also it is possible to use the TS pin to control counting of time. This is typically for use

with the stop-watch mode where an elapsed time counter function can be implemented.

Using the STOPM bit in the Function register (see Table 50) it is possible to control the

STOP bit by the TS pin.

7.12.6 INTAPM[1:0]: INTA pin mode control

Bit

Symbol

Value

Description

INTA pin mode

00 [1]

CLK output mode

battery mode indication

INTA output

1 to 0

INTAPM[1:0]

Hi-Z

Table 48. INTAPM[1:0] bits - Pin_IO control register (address 27h)

[1]

Default value.

The INTA pin can be used to output three different signals.

INTA (CLK)

battery mode

clock data

INTA data

aaa-010464

Figure 30. INTA pin

7.12.6.1 INTAPM[1:0]: INTA

The primary function of the INTA pin is to output INTA data. INTA data is controlled by the

bits of the INTA_enable register (see Table 28).

The output is active LOW with an open-drain output. The output is available during VDD

and VBAT operation.

7.12.6.2 INTAPM[1:0]: clock data

It is possible to output a clock frequency on the INTA pin. Clock frequency is selected

with the COF[2:0] bits in the Function register (Section 7.13). The output is active LOW

with an open-drain output. The output is available only during VDD operation. The output

is Hi-Z when operating from VBAT.

PCF85263A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 1 February 2021

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PCF85263ATL/A Datasheet(PDF) 48 Page - NXP Semiconductors

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