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APPLICATION INFORMATION

CLOSED-LOOP POWER STAGE CHARACTERISTICS

POWER SUPPLIES

DEVICE PROTECTION SYSTEM

TAS5601

SLAS585 – FEBRUARY 2008

The TAS5601 is PWM input power stage with a closed loop architecture. A 2nd order feedback loop varies the

PWM output duty cycle with changes in the supply voltage. This ensures that the output voltage (and output

power) remain the same over transitions in the power supply.

Open-loop power stages have an output duty cycle that is equal to the input duty cycle. Since the duty cycle

does NOT change to compensate for changes in the supply voltage, the output voltage (and power) change with

supply voltage changes. This is undesirable effect that closed-loop architecture of the TAS5601 solves.

The single-ended (SE) gain of the TAS5601 is fixed, and specified below:

TAS5601 Gain = 0.13 / Modulation Level (Vrms/%)

Modulation level = fraction of full-scale modulation of the PWM signal at the input of the power stage.

TAS5601 (SE) Voltage Level (in Vrms) = 0.13 x Modulation Level

The bridge-tied (BTL) gain of the TAS5601 is equal to 2x the SE gain:

TAS5601 (BTL) Voltage Level (in Vrms) = 0.26 x Modulation Level

For a digital modulator like the TAS5706, the default maximum modulation limit is 97.7%. For a full scale input,

the PWM output switches between 2.3% and 97.7%. This equates to a modulation level of 95.4% for a full scale

input (0 dBFS).

For example, calculate the output voltage in RMS volts given a –20 dBFS signal to a digital modulator with a

maximum modulation limit of 97.7% in a BTL output configuration:

TAS5601 Output Voltage = 0.1 (–20dB) x 0.26 (Gain) x 95.4 (Modulation Level)

= 2.48 Vrms

It is also important to maintain a switching signal at the PWM inputs of the TAS5601 while the RESET terminal is

held HIGH (>1.9V). If a switching signal is not maintained on the inputs under the previous condition, a loud

“pop” can occur in the speaker. The TAS5601 is not compatible with modulators that hard mute the outputs

(output go to LOW-LOW state). For MUTE case, the modulator needs to hold outputs switching at 50% duty

cycle.

For power-up, ensure that the PWM inputs are switching before RESET is transitioned HIGH (>1.9V). For

shutdown and power-down, the PWM inputs should remain switching for the “turn-off” time specified in the DC

Electrical Characteristics table. For SE mode, this is approximately 500ms. For BTL mode, the time is much

faster, at 30ms. This ensures the best “pop” performance in the system.

To allow simplified system design, the TAS5601 requires only a single supply (PVCC) for the the power blocks

and a 3.3 V (DVDD) supply for PWM input blocks. In addition, the high-side gate drive is provided by built-in

bootstrap circuits requiring only an external capacitor for each half-bridge.

In order for the bootstrap circuit to function properly, it is necessary to connect a small ceramic capacitor from

each bootstrap pin (BS_) to the corresponding output pin (OUT_). When the power-stage output is low, the

bootstrap capacitor is charged through an internal diode. When the power-stage output is high, the bootstrap

capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the

high-side gate drive.

The TAS5601 contains a complete set of protection circuits carefully designed to make system design efficient as

well as to protect the device against any kind of permanent failures due to short circuits, overload,

overtemperature, and undervoltage.

Copyright © 2008, Texas Instruments Incorporated

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