 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MIC2131 Datasheet(PDF) 16 Page - Micrel Semiconductor |
|
|
|||||||||||||||||||||||||||||
MIC2131 Datasheet(HTML) 16 Page - Micrel Semiconductor |
|
|
16 / 20 page  Micrel, Inc. MIC2130/1 April 2008 16 M9999-042108-C Control Loop Stability and Compensation Figure 10 shows the simplified system schematic. The internal transconductance error amplifier is used for compensating the voltage feedback loop by placing a capacitor (C1) in series with a resistor (R1) and another capacitor C2 in parallel from the COMP pin-to-ground. (Note: Ceramic output caps may require type III compensation). R1 C1 C2 gm VREF VFB VCOMP D (s) VRAMP RHS RLS VIN VOUT RESR RLOAD C PWM Comparator L VSW Figure 10 Simplified System Schematic In order to have a stable system when the gain of T(s) = 1 ⇒ (0db) the phase has to be greater (less negative) than -180°. The amount the phase is greater than -180° is called the phase margin, typically 30 to 60 and is a key parameter predicting the stability of the system and how much overshoot and undershoot the system exhibits during transients. The open loop transfer function is: T(s) = Gea(s) x GPWMcomp(s) x GPwrs(s) x Gflt(s) x Hfb(s) And the phase is: fb Flt PwrS PWMcomp ea T θ θ θ θ θ (s) θ T(s) + + + + = = ∠ VREF VFB VOUT Gea(s) = gm ZCOMP GPWMComp GPWRS GFLT H(s) VE VCOMP D (s) VSW T(s) Figure 11 System Block Diagram In the system block diagram in figure 11 Gea(s) = gm x Zcomp Gain of the Error amp where gm =1.5ms and ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + = 2 1 comp sC 1 sC 1 R1 Z 0.85 1.1 2.1 0.85 ∆V D ∆V ∆D (s) G ramp Max comp PWMcomp = − = = = Gain of the PWM comparator D * D V D * ∆d(s) V ∆d(s) ∆V (s) G Max Out Out SW PwrS = = = Gain of the Power Stage 2 0 2 0 out esr Flt ω s Qω s 1 C sR 1 (s) G + + + = Gain of the Filter where: out Load Lost stored L/C R E E Q = = (Parallel loaded) and out 0 LC 1 ω = out esr esr C R 2π 1 F = out ref HS LS LS V V R R R H(s) = + = Gain of the feedback network For simplicity, combine the PWM comparator gain and the Power stage gain and call it the modulator gain. D * ∆V V D * D V * ∆V D (s) G * (s) G (s) G ramp out Max out ramp Max PWRsw PWMcomp Mod = = = therefore; T(s) = Gea(s) x GMod(s) x Gflt(s) x Hfb(s) and fb flt Mod ea T θ θ θ θ (s) θ + + + = The phase of the open loop is the phase of all the blocks in the loop added together. The phase of T(s) is fb Flt PwrS PWMcomp ea T θ θ θ θ θ (s) θ + + + + = fb Mod ea T θ θ θ (s) θ + + = Where pole1 Zero1 pole0 ea θ θ θ θ − + − = pole0 θ = phase lag due to the pole at the origin Zero1 θ =phase lead due to Zero1 pole1 θ = phase lag due to pole1 ° = 0 θ PWMcomp , ° = 0 θ PwrS ° = 0 θ fb therefore; ° = 0 θ Mod The phase of the filter includes the complex poles of LC and the Zero caused by the ESR of the COUT. The filter has 2 poles at 0 F and a zero at esr F ° − = 180 θ Flt at 0 F and +90° at esr F |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
