DRA752ABC datasheet(168/443 Pages) TI2

168 / 443 page

168

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Specifications

Table 5-9. Maximum Supported Frequency (continued)

Module

Clock Sources

Instance Name

Input Clock Name

Clock

Type

Max. Clock

Allowed (MHz)

PRCM Clock Name

PLL / OSC /

Source Clock

Name

PLL / OSC /

Source Name

WD_TIMER2

WD_TIMER2_ICLK

Int

38.4

WKUPAON_GICLK

SYS_CLK1

OSC1

DPLL_ABE_X2_CL

DPLL_ABE

WD_TIMER2_FCL

Func

0.032

WKUPAON_SYS_GFC

WKUPAON_32K_G

FCLK

RTC Oscillator

5.6

Power Consumption Summary

NOTE

Maximum power consumption for this SoC depends on the specific use conditions for the

end system. Contact your TI representative for assistance in estimating maximum power

consumption for the end system use case.

5.7

Electrical Characteristics

NOTE

The data specified in Section 5.7.1 through Section 5.7.14 are subject to change.

NOTE

The interfaces or signals described in Section 5.7.1 through Section 5.7.14 correspond to the

interfaces or signals available in multiplexing mode 0 (Function 1).

All interfaces or signals multiplexed on the balls described in these tables have the same DC

electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which

case different DC electrical characteristics are specified for the different multiplexing modes

(Functions).

5.7.1

LVCMOS DDR DC Electrical Characteristics

Table 5-10 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.

NOTE

For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control

Module of the Device TRM.

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