DRA752ABC datasheet(170/443 Pages) TI2

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170

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Specifications

Table 5-10. LVCMOS DDR DC Electrical Characteristics (continued)

PARAMETER

MIN

NOM

MAX

UNIT

VIL

Low-level input threshold

DDR3/DDR3L

-0.2

VREF-0.1

DDR2

-0.3

VREF-0.125

VCM

Input common-mode voltage

VREF

-10%vdds

VREF+

10%vdds

CPAD

Pad capacitance (including package capacitance)

Differential Receiver Mode

VSWING

Input voltage swing

DDR3/DDR3L

0.2

vdds+0.4

DDR2

0.25

vdds+0.6

VCM

Input common-mode voltage

VREF

-10%vdds

VREF+

10%vdds

CPAD

Pad capacitance (including package capacitance)

(1) VDDS stands for corresponding power supply (that is vdds_ddr1 or vdds_ddr2). For more information on the power supply name and

the corresponding ball, see Table 4-2, POWER [11] column.

(2) VREF in this table stands for corresponding Reference Power Supply (that is ddr1_vref0 or ddr2_vref0). For more information on the

power supply name and the corresponding ball, see Table 4-2, POWER [11] column.

5.7.2

HDMIPHY DC Electrical Characteristics

The HDMIPHY DC Electrical Characteristics are compliant with the HDMI 1.4a specification and are not

reproduced here.

5.7.3

Dual Voltage LVCMOS I2C DC Electrical Characteristics

Table 5-11 summarizes the DC electrical characteristics for Dual Voltage LVCMOS I2C Buffers.

NOTE

For more information on the I/O cell configurations, see the Control Module section of the

Device TRM.

Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics

PARAMETER

MIN

NOM

MAX

UNIT

Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda;

Balls: F17 / C20 / C21 / C25

I2C Standard Mode – 1.8 V

VIH

Input high-level threshold

0.7*VDDS

VIL

Input low-level threshold

0.3*VDDS

Vhys

Hysteresis

0.1*VDDS

IIN

Input current at each I/O pin with an input voltage

between 0.1*VDDS to 0.9*VDDS

µA

IOZ

IOZ(IPAD Current) for BIDI cell. This current is

contributed by the tristated driver leakage + input

current of the Rx + weak pullup/pulldown leakage.

PAD is swept from 0 to VDDS and the Max(I(PAD))

is measured and is reported as IOZ

µA

CIN

Input capacitance

VOL3

Output low-level threshold open-drain at 3-mA

sink current

0.2*VDDS

IOLmin

Low-level output current @VOL=0.2*VDDS

tOF

Output fall time from VIHmin to VILmax with a bus

capacitance CB from 5 pF to 400 pF

250

I2C Fast Mode – 1.8 V

VIH

Input high-level threshold

0.7*VDDS

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