DRA752ABC datasheet(181/443 Pages) TI2

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181

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

www.ti.com

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Specifications

ms. All “Tn” markers show total elapsed time from T0.

(2) Terminology:

–

VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4,

Recommended Operating Conditions.

–

Ramp Up = transition time from VOFF to VOPR MIN.

(3) General timing diagram items:

–

Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.

–

Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in

associated note.

–

Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power sequencer circuit performance.

(4) vddshv5, vdd_rtc, and vdda_rtc domains:

–

If RTC mode is used, then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be

combined with other rails.

–

If RTC-mode is not supported then the following combinations are approved:

–

vdda_rtc can be combined with vdds18v

–

vdd_rtc can be combined with vdd

–

vddshv5 can be combined with other 1.8 V or 3.3 V vddshvn rails

If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing

requirements.

(5) vdda_* rails should not be combined with vdds18v_* for best performance to avoid transient switching noise impacts on analog domains.

vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached

until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an

inadvertent violation.

(6) vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence has vdds_ddr1 following vdds18v_* to ensure circuit

components and PCB design do not cause an inadvertent violation. vdds_ddr1 can ramp-up before, concurrently or after vdda_*, there

are no dependencies between vdds_ddr1 and vdda_* domains:

–

For DDR2 mode of operation (1.8 V), vdds_ddr1 supplies can be combined with all vdds18v_* supplies and ramped up together for

simplified PDN and power sequencing.

–

If vdds_ddr1 is combined with vdds18v_ddr1 but kept separate from vdds18v on board, then this combined 1.8 V DDR supply can

come up together or after the vdds18v supply. The 1.8 V DDR supply should never ramp up before the vdds18v.

(7) vdd should not ramp-up before vdds18v_* or vdds_ddr* domains have reached VOPR MIN.

(8) vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains should follow vdd core supply as preferred sequence. If vdd_mpu, vdd_iva, vdd_gpu,

vdd_dspeve domains ramp concurrently or quicker than vdd core, then vdd core must remain at least 150 mV greater than vdd_mpu,

vdd_iva, vdd_gpu, vdd_dspeve domains during ramp. Circuit design (components and PCB) must ensure vdd reaches final operational

voltage before any of the vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains.

(9) VDDA_PHY group should not be combined with VDDA_PLL group to avoid transient switching noise impacts.

(10) vddshv[1-4, 6, 7, 9-11] domains:

–

If 1.8 V I/O signaling is needed, then 1.8 V must be sourced from common vdds18v supply and ramp up concurrently with vdds18v.

–

If 3.3 V I/O signaling is needed, then 3.3 V vddshvx rails must ramp up after vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve, and

VDDA_PHY group domains.

(11) vdda33v_usb[1-2] domain:

–

If USB1 and USB2 interfaces are used, should be supplied from independent analog supply.

–

If USB1/USB2 interface is not used, could be connected to VSS/GND if both conditions are met:

–

USB1/USB2 diff pair (usb1_dm/usb1_dp; usb2_dm/usb2_dp) pins are left unconnected

–

vdda_usb1 and/or vdda_usb2 PHY is not energized

(12) vddshv8 shows two ramp up options for 1.8 V I/O or 3.3 V I/O or SD Card operation:

–

If 1.8 V I/O signaling is needed, then vddshv8 must ramp up after vdd and before or concurrently with 3.3 V vddshv* rails.

–

If 3.3 V I/O signaling is needed, then vddshv8 must be combined with other 3.3 V vddshv* rails.

–

If SD Card operation is needed, then vddshv8 must be sourced from a dual voltage (3.3 V / 1.8 V) power source per SDIO

specifications and ramp up concurrently with 3.3 V vddshv* rails.

(13) Pulse duration: rtc_porz must remain low 1 ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable or can be de-asserted

before but no later than porz. The FUNK_32K_CLK source must be stable and at a valid frequency 1 ms prior to de-asserting rtc_porz

high.

(14) porz must remain asserted low until both of the following conditions are met:

–

Minimum of 12 × P, where P = 1 / (SYS_CLK1 / 610), units in ns.

–

All device supply rails reach stable operational levels.

(15) Setup time: sysboot[15:0] pins must be valid 2P(14) before porz is de-asserted high.

(16) Hold time: sysboot[15:0] pins must be valid 15P(14) after porz is de-asserted high.

(17) rstoutn will be set high after global reset, due to porz, is de-asserted following an internal 2 ms delay. rstoutn is only valid after vddshv3

reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches

during power up.

DRA752ABC Datasheet(PDF) 181 Page - Texas Instruments

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