DRA752ABC datasheet(182/443 Pages) TI2

182 / 443 page

vdds18v, vdds_mlbp, vdds18v_ddr1,

vdds18v_ddr2

vdda_abe_per, vdda_ddr, vdda_debug,

vdda_dsp_eve, vdda_gmac_core,

vdda_gpu, vdda_iva, vdda_video,

vdda_mpu, vdda_osc

(VDDA_PLL Group)

vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie,

vdda_pcie0, vdda_pcie1, vdda_sata, vdda_usb3

(VDDA_PHY Group)

vdds_ddr1,

ddr1_vref0, ddr2_vref0

vdds_ddr2,

vdd

vdd_mpu

vdd_gpu

vdd_dspeve

vdd_iva

vddshv8

vddshv1, vddshv2, vddshv3, vddshv4, vddshv6,

vddshv7, vddshv9, vddshv10, vddshv11

vdda33v_usb1, vdda33v_usb2

porz

xi_osc0

vddshv5

vdd_rtc

vdda_rtc

SPRS85v_ELCH_02

Note 4

Note 5

Note 7

Note 8

Note 9

Note 10

Note 11

Note 12

Note 8

Note 13

Note 9

Note 8

Note 14

Note 6

rtc_porz

Note 8

∆TD1

182

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Specifications

Figure 5-3. Recommended Power-Down Sequencing

(1) Time stamps:

–

T0 = 0 ms, T1 > 100 μs, T2 = 0.5 ms, T3 = 1.0 ms, T4 = 1.5 ms; V1 = 2.7 V. All “Tn” markers are intended to show elapsed times

from T0. Delta time: Δ TD1 > 100 μs.

(2) Terminology:

–

VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4,

Recommended Operating Conditions.

–

VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.

–

Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.

(3) General timing diagram items:

DRA752ABC Datasheet(PDF) 182 Page - Texas Instruments

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