DRA752ABC datasheet(186/443 Pages) TI2

186 / 443 page

SPRS85v_ELCH_06

vdd_dspeve, vdd_gpu, vdd_iva,

vdd_mpu, vdd, vdd_rtc

xi_osc0

porz, rtc_porz

V10

V11

Tdelta2

vdds_ddr1, ddr1_vref0

Tdelta1

Note 9, Note 11

Note 4

Note 9

Note 9, Note 10

Note 12

vdda_per, vdda_ddr, vdda_debug,

vdda_gmac_core, vdda_gpu, vdda_video,

vdda_osc, vdda_mpu, vdda_usb[1-3],

vdda_hdmi, vdda_pcie, vdda_rtc

vddshv[1-7, 9-11]

vddshv5, vddshv8

vdda33v_usb[1-2]

(5)

(8)

(7)

vddshv[1-7, 9-11]

vdds18v, vdds_mlbp, vdds18v_ddr1

(6)

SPRS916_ELCH_05

vdds18v

Note 1

Note 2

vdda_*

186

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Specifications

Figure 5-7. vdds18v and vdda_* Discharge Relationship(3)

(1) vdda_* can be

≥ vdds18v, until vdds18v drops below 1.62 V.

(2) vdds18v must be

≥ vdda_*, until vdds18v reaches 0.6 V.

(3) V1 = 1.62 V; V2 < 0.6 V.

Figure 5-5 through Figure 5-8 and associated notes described the device abrupt power down sequence.

A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally,

the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of

elapsed time. This is the typical range of elapsed time available following a loss of power event, see

Section 8.3.7 for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power

down sequence can be supported without impacting POH reliability if all of the following conditions are

met (Figure 5-8).

Figure 5-8. Abrupt Power-Down Sequencing(1)

(1) Time stamps:

–

V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs;

Tdelta2 < 10 ms.

DRA752ABC Datasheet(PDF) 186 Page - Texas Instruments

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