DRA752ABC datasheet(183/443 Pages) TI2

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183

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

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SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Specifications

–

Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.

–

Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in

associated note.

–

Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit

performance.

(4) porz signals must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp

down.

(5) vddshv* domains supplied by 3.3 V:

–

must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.

–

must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.

–

must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-7 “vdds18v and vdda_* Discharge Relationship”.

(6) vddshv* domains supplied by 1.8 V:

–

must ramp down concurrently with vdds18v and be sourced from the same vdds18v supply.

(7) vddshv8 domain:

–

must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.

–

if SDIO operation is needed, must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V)

operation as required to be compliant to SDIO specification

–

if SDIO operation is not needed, must be grouped and ramped down with other vddshv* domains as noted above.

(8) RTC domains (vddshv5, vdd_rtc, and vdda_rtc):

–

If RTC mode is used:

–

rtc_porz can be asserted low before porz and RTC domains can be ramped down after 100 µs elapsed time.

–

must be sourced from independent supplies and must not be combined with other rails.

–

timing diagram shows this mode of operation.

–

If RTC mode is not used, then:

–

rtc_porz must be connected to porz signal.

–

vddshv5 must be grouped and ramped down with other vddshv* domains as noted above.

–

vdd_rtc must be grouped and ramped down with vdd.

–

vdda_rtc must be grouped and ramped down with either VDDA_PHY group or vdds18v.

(9) vdda_* domains:

–

should not be combined with vdds18v for best performance to avoid transient switching noise impacts on analog domains.

–

can ramp down before or concurrently with vdds18v.

–

must satisfy the vdds18v and vdda_* Discharge Relationship (see Figure 5-7) if vdda_* disable point is later or discharge rate is

slower than vdds18v.

–

can ramp down before, concurrently or after vdds_ddr*, there is no dependency between these supplies.

(10) vdda33v_usb* domains:

–

can start ramping down 100 µs after low assertion of porz

–

can ramp down concurrently or before VDDA_PHY group

(11) vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains can ramp down before or concurrently with vdd.

(12) vdd can ramp down concurrently or after with vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains.

(13) vdds_ddr* domains:

–

should ramp down after vdd begins ramping down.

–

If DDR2 memory is used (requiring 1.8 V supply):

–

then vdds_ddr* can be combined with vdds18v and vdds18v_ddr* domains and sourced from a common supply. Accordingly, all

domains can ramp down concurrently with vdds18v

–

if vdds_ddr* and vdds18v_ddr* are combined but kept separate from vdds18v, then the combined 1.8 V DDR supply can ramp

down before or concurrently with vdds18v

(14) vdds18v domain:

–

should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.

–

must satisfy the vdds18v versus vddshv[1-7, 9-11] Discharge Relationship (see Figure 5-5) if vddshv* is operating at 3.3 V

–

must satisfy the vdds18v and vdds_ddr* Discharge Relationship (see Figure 5-6) if vdds_ddr* discharge rate is slower than vdds18v.

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