DRA752ABC datasheet(185/443 Pages) TI2

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vdds18v

vdds_ddr1, vdds_ddr2

SPRS85v_ELCH_04

vddshv1, vddshv2, vddshv3,

vddshv4, vddshv6, vddshv7,

vddshv9, vddshv10, vddshv11,

vddshv8

(Note 2)

vdds18v

Vdelta

(Note1)

SPRS85v_ELCH_06

185

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

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SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Specifications

(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.

(3) vdd must ramp down after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.

(4) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.

(5) vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.

(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.

(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn

rails but vddshv8 must ramp down before vdd and must ramp up after vdd.

(8) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.

vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If

vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must ensure that the vddshvn rail is never higher

than 2.0 V above the vdds18v rail.

(9) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp

down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other

vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

Figure 5-5 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.

Figure 5-5. vdds18v versus vddshv[1-7, 9-11] Discharge Relationship

(1) Vdelta MAX = 2V

(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.

If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr*

discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time

period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is

less than 10 ms (Figure 5-6).

Figure 5-6. vdds18v and vdds_ddr* Discharge Relationship(1)

(1) V1 > 1.0 V; V2 < 0.6V; T1 < 10ms.

DRA752ABC Datasheet(PDF) 185 Page - Texas Instruments

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