DRA752ABC datasheet(187/443 Pages) TI2

187 / 443 page

187

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

www.ti.com

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

Submit Documentation Feedback

Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Specifications

(2) Terminology:

–

VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4,

Recommended Operating Conditions table.

–

VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.

–

Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.

(3) General timing diagram items:

–

Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.

–

Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit

performance.

(4) porz and rtc_porz must be asserted low for 100 μs min to ensure SoC is set to a safe functional state before any voltage begins to ramp

down.

–

Only if using RTC-mode with an independent RTC input power source, then rtc_porz can remain high and RTC-domains (vdd_rtc,

vdda_rtc, and vddshv5) can remain energized while all other domains sourced from the system input power are powered down.

(5) vddshv[1-7, 9-11] domains supplied by 3.3 V:

–

must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 μs min, after porz is asserted low.

–

must not exceed vdds18v voltage level by more than 2 V during ramp down, until vdds18v drops below VOFF (0.6 V).

(6) vddshv[1-7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.

(7) vddshv8 supporting SD Card:

–

must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.

–

must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be

compliant to SDIO specification.

–

if SDIO operation is not needed, must be grouped with other vddshv[1-7, 9-11] domains.

(8) vdda33v_usb[1-2] domains must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.

(9) vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu, vdd, vdd_rtc, vdds_ddr1, vdda_* domains can all start to ramp down in any order after 100 µs

low assertion of porz.

(10) vdds_ddr1 domains:

–

can remain at VOPR MIN or a level greater than vdds18v during ramp down.

–

elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.

(11) vdda_* domains:

–

can start to ramp down before or concurrently with vdds18v.

–

must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).

(12) vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dspeve and vdd start to ramp down.

DRA752ABC Datasheet(PDF) 187 Page - Texas Instruments

DRA752ABC Datasheet(HTML) 187 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL