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DRA752ABC Datasheet(PDF) 134 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 134 Page - Texas Instruments |
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134 / 443 page  134 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-28. Sysboot Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL sysboot4 Boot Mode Configuration 4. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L6 sysboot5 Boot Mode Configuration 5. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L4 sysboot6 Boot Mode Configuration 6. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L3 sysboot7 Boot Mode Configuration 7. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L2 sysboot8 Boot Mode Configuration 8. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L1 sysboot9 Boot Mode Configuration 9. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I K2 sysboot10 Boot Mode Configuration 10. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I J1 sysboot11 Boot Mode Configuration 11. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I J2 sysboot12 Boot Mode Configuration 12. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I H1 sysboot13 Boot Mode Configuration 13. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I J3 sysboot14 Boot Mode Configuration 14. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I H2 sysboot15 Boot Mode Configuration 15. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I H3 4.4.25.2 Power, Reset, and Clock Management (PRCM) NOTE For more information, see PRCM section of the device TRM. Table 4-29. PRCM Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL clkout1 Device Clock output 1. Can be used externally for devices with non-critical timing requirements, or for debug, or as a reference clock on GPMC as described in Table 7-26, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 7-28, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate. O F21 / P7 clkout2 Device Clock output 2. Can be used externally for devices with non-critical timing requirements, or for debug. O D18 / N1 clkout3 Device Clock output 3. Can be used externally for devices with non-critical timing requirements, or for debug. O C23 rstoutn Reset out (Active low) output is asserted low whenever any global reset condition exists. After a brief delay, it will be set high upon removal of the internal global reset condition (porz, warm reset). It is only functional after its output buffer’s reference voltage (vddshv3) is valid. If it is used as a reset for device peripheral components, then it should be AND gated with porz to avoid the possibility of reset signal glitches during a power up sequence.(2) O F23 resetn Reset (active low) input’s falling edge can trigger a device warm reset state from an external component. This signal should be high prior to or simultaneous with, porz rising. If the signal is not used in the system, resetn should be pulled high with an external pull-up resistor to vddshv3. I E23 porz Power on Reset (active low) input must be asserted low during a device power up sequence or cold reset state when all supplies are disabled. Typically, an external PMIC is the source and sets porz high after all supplies reach valid operating levels. Asserting porz low puts the entire device in a safe reset state. I F22 |
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