DRA752ABC datasheet(135/443 Pages) TI2

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DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

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SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Terminal Configuration and Functions

Table 4-29. PRCM Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

BALL

xref_clk0

External Reference Clock 0. For Audio and other Peripherals.

D18

xref_clk1

External Reference Clock 1. For Audio and other Peripherals.

E17

xref_clk2

External Reference Clock 2. For Audio and other Peripherals.

B26

xref_clk3

External Reference Clock 3. For Audio and other Peripherals.

C23

xi_osc0

System Oscillator OSC0 Crystal input / LVCMOS clock input. Functions as the input

connection to a crystal when the internal oscillator OSC0 is used. Functions as an

LVCMOS-compatible input clock when an external oscillator is used.

AE15

xo_osc0

System Oscillator OSC0 Crystal output

AD15

xi_osc1

Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input. Functions as the

input connection to a crystal when the internal oscillator OSC1 is used. Functions as

an LVCMOS-compatible input clock when an external oscillator is used

AC15

xo_osc1

Auxiliary Oscillator OSC1 Crystal output

AC13

RMII_MHZ_50_C

LK(1)

RMII Reference Clock (50MHz). This pin is an input when external reference is used

or output when internal reference is used.

(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the

clock input. Any non-monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.

(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it

must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.

4.4.25.3 Real Time Clock (RTC) Interface

NOTE

For more information, see the Real Time Clock (RTC) SS section of the device TRM.

Table 4-30. RTC Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

Wakeup0

RTC External Wakeup Input 0

AD17

Wakeup1

RTC External Wakeup Input 1

AC17

Wakeup2

RTC External Wakeup Input 2

AB16

Wakeup3

RTC External Wakeup Input 3

AC16

rtc_porz

RTC Power Domain Power-On Reset Input

AB17

rtc_osc_xi_clkin3

RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as an

RTC clock input when an external oscillator is used.

AE14

rtc_osc_xo

RTC Oscillator Output

AD14

rtc_iso(1)

RTC domain isolation signal.

AF14

on_off

RTC Power Enable output pin

Y11

(1) This signal must be kept 0 if device power supplies are not valid during RTC mode and 1 during normal operation. This can typically be

achieved by connecting rtc_iso to the same signal driving porz (not rtc_porz) with appropriate voltage level translation if necessary.

4.4.25.4 System Direct Memory Access (SDMA)

NOTE

For more information, see the DMA Controllers / System DMA section of the device TRM.

Table 4-31. SDMA Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

dma_evt1

System DMA Event Input 1

P7 / P4

dma_evt2

System DMA Event Input 2

N1 / R3

dma_evt3

System DMA Event Input 3

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