L6711 datasheet(44/50 Pages) STMICROELECTRONICS

44 / 50 page

Layout guidelines

L6711

44/50

Layout guidelines

Since the device manages control functions and high-current drivers, layout is one of the

most important things to consider when designing such high current applications.

A good layout solution can generate a benefit in lowering power dissipation on the power

paths, reducing radiation and a proper connection between signal and power ground can

optimize the performance of the control loops.

Integrated power drivers reduce components count and interconnections between control

functions and drivers, reducing the board space.

Here below are listed the main points to focus on when starting a new layout and rules are

suggested for a correct implementation.

18.1

Power connections.

These are the connections where switching and continuous current flows from the input

supply towards the load. The first priority when placing components has to be reserved to

this power section, minimizing the length of each connection and loop as much as possible.

To minimize noise and voltage spikes (EMI and losses) these interconnections must be a

part of a power plane and anyway realized by wide and thick copper traces: loop must be

anyway minimized. The critical components, i.e. the power transistors, must be located as

close as possible one to the other.

Figure 23 shows the details of the power connections involved and the current loops. The

input capacitance (CIN), or at least a portion of the total capacitance needed, has to be

placed close to the power section in order to eliminate the stray inductance generated by

the copper traces. Low ESR and ESL capacitors are preferred.

Use as much VIAs as possible when power traces have to move between different planes

on the PCB: this reduces both parasitic resistance and inductance. Moreover, reproducing

the same high-current trace on more than one PCB layer will reduce the parasitic resistance

associated to that connection.

Connect output bulk capacitor as near as possible to the load, minimizing parasitic

inductance and resistance associated to the copper trace also adding extra decoupling

capacitors along the way to the load when this results in being far from the bulk capacitor

bank.

Figure 23.

Power connections and related connections layout guidelines (same for

all phases).

CIN

VIN

UGATEx

PHASEx

LGATEx

PGNDx

LOAD

BOOTx

PHASEx

VCC

SGND

+Vcc

CIN

VIN

LOAD

To limit C

BOOT

Extra-Charge

a. PCB power and ground planes areas

b. PCB small signal components placement

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